Cache Access Rights and Ownership Transition Independence
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Solution Overview
Problem
Current cache coherency protocols in multiprocessor systems, such as snooping and directory-based protocols, suffer from high latency and complexity, particularly in systems with out-of-order execution, prefetching, multiple cores, and multi-threading, due to the requirement that access rights of processors change in the order of received requests and the need for acknowledgment messages.
Innovation Solution
A computer system where access rights and ownership responsibilities for cache blocks transition independently, with access rights transitioning upon receipt of data packets and ownership responsibilities transitioning upon receipt of address packets, allowing for separate timing and enabling the system to inhibit data packet receipt based on a timestamp associated with the data packet.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If access rights change in the order of received snoops, then cache consistency is maintained, but latency increases for out-of-order execution processors
Solution Approach 1:
The patent segments the cache access rights into two independent components: ownership responsibility (which processor owns the data) and access rights (what operations are permitted). This segmentation allows these two aspects to transition independently, resolving the contradiction by enabling access rights to change out of order while maintaining ownership consistency through separate tracking mechanisms.
2Reliability
If standard snooping protocol is used, then cache coherency is maintained, but device complexity increases due to acknowledgment requirements
Solution Approach 1:
The patent extracts the acknowledgment mechanism from the core coherency protocol. By separating ownership tracking from access right validation, the system eliminates the need for complex acknowledgment messages while maintaining coherency through the independent ownership responsibility field that naturally tracks data location without requiring additional communication overhead.
3Device complexity
If access rights and ownership transition together, then protocol simplicity is maintained, but productivity decreases for multi-threaded processors
Solution Approach 1:
The patent introduces dynamic independence between access rights and ownership transitions. The system allows access rights to be granted or revoked without requiring simultaneous ownership transitions, enabling multi-threaded processors to operate more efficiently by reducing synchronization barriers while the protocol remains simple through the clear separation of these two state components.
Data Source
AI summary
A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.