Multi-core Cache Data Replacement Using Access Statistics
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Solution Overview
Problem
In multi-core communication processors, the existing data replacement algorithms, such as LRU, fail to optimize cache hit rates effectively, leading to decreased CPU efficiency when data packets are frequently replaced, causing bottlenecks and reduced performance due to the need to access slower DDR memory instead of the system cache.
Innovation Solution
A method and multi-core communication processor that calculates an access statistics value for each header data packet, representing the difference between a predetermined number of access times and actual access times by CPUs, to identify and transfer header data with the lowest access statistics value to external memory, thereby increasing the likelihood of retaining high-priority data packets in the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LRU algorithm is used for data replacement in system cache, then data packets are replaced based on least recently used criterion, but cache hit rate is not optimized effectively causing CPU to access slower DDR memory
Solution Approach 1:
The patent changes the replacement criterion from time-based (LRU) to a composite parameter including access frequency, access time, and data priority. This parameter transformation enables more intelligent selection of data to retain in cache, directly improving cache hit rate and preventing CPU efficiency degradation.
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors access statistics (access frequency, access time) and dynamically adjusts replacement decisions. This feedback loop ensures that data with high access probability remains in cache, optimizing both cache hit rate and CPU processing efficiency.
2Quantity of substance
If system cache capacity is limited, then new data packets must replace old data packets, but frequent replacement causes CPU to miss data in cache and access slower DDR memory
Solution Approach 1:
The patent transforms the single-dimensional cache management (simple LRU) into multi-dimensional management by incorporating access frequency, access time, and data priority parameters. This enables more accurate prediction of data reuse probability, reducing premature eviction of frequently accessed data and minimizing CPU access time to DDR memory.
Solution Approach 2:
The patent performs preliminary evaluation of data packets using access statistics before replacement occurs. By calculating access frequency and time patterns in advance, the system identifies data likely to be accessed soon and prioritizes its retention, preventing time loss from DDR memory access.
3Productivity
If data packets are continuously written into system cache from network port, then cache becomes full and old data packets are transferred to DDR, but CPU efficiency decreases when data must be fetched from DDR
Solution Approach 1:
The patent uses access statistics feedback (access frequency, access time) to dynamically control data retention decisions. This feedback mechanism ensures that data packets likely to be accessed soon are prioritized for retention in the high-speed cache, maintaining both processing throughput and access speed by preventing unnecessary DDR memory fetches.
Data Source
AI summary
A method for replacing data in a system cache includes obtaining, by the system cache, an access statistics value corresponding to each piece of header data in the system cache, wherein the access statistics value corresponding to the header data represents a difference of the predetermined number of access times of the header data minus the number of times that the header data has been accessed by central processing units (CPUs); obtaining, by the system cache according to the access statistics value corresponding to each piece of header data, header data to be transferred; and transferring, by the system cache, the header data, which is to be transferred, to an external memory.