Processor Cache Accounting Bits for Trace File Size Reduction

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Solution Overview

Problem

Existing debugging techniques face challenges in efficiently recording and storing trace files of code execution due to large file sizes, which consume significant storage resources and affect performance.

Innovation Solution

The use of a processor cache with accounting bits, including unit bits and reference bits, to efficiently record and store trace files by logging only necessary data, reducing file sizes significantly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional debugging trace recording methods are used, then complete execution traces can be captured, but trace file sizes become very large consuming significant storage resources

Engineering Contradiction:
Improvetrace completenessVSAvoidtrace file size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the essential information needed for debugging from the complete execution trace. Instead of recording all cache line values, it records only the cache line addresses and uses a separate cache structure to store the actual values, thereby separating the trace metadata from the trace data and significantly reducing the trace file size while maintaining debugging capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a copy of the processor cache in the form of a trace cache structure that stores cache line values. This copy allows the trace file to reference cache lines by address rather than storing duplicate value data, reducing trace file size while preserving the ability to replay and analyze execution traces

Inventive Principle:
Principle #26Copying

2Measurement precision

If complete execution traces are recorded, then debugging accuracy is maintained, but storage resources are significantly consumed

Engineering Contradiction:
Improvedebugging accuracyVSAvoidstorage resources
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent segments the trace recording system into two parts: a compact trace file that records execution events with cache line addresses, and a separate trace cache structure that stores the actual cache line values. This segmentation allows the trace file to remain small while the trace cache preserves debugging accuracy by maintaining the full cache state when needed

Inventive Principle:
Principle #1Segmentation

3Reliability

If all cache values are logged in the trace file, then complete execution replay is possible, but trace file performance deteriorates

Engineering Contradiction:
Improveexecution replay accuracyVSAvoidtracing performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the bulk cache value data from the trace file and stores it in a separate trace cache structure. The trace file only contains lightweight references (cache line addresses), which dramatically reduces the amount of data that needs to be written to and read from the trace file, thereby improving tracing performance while maintaining execution replay accuracy through the separate cache structure

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11016891B2Facilitating recording a trace file of code execution using a processor cache
Publication Date: 2021.05.25 MICROSOFT TECHNOLOGY LICENSING LLC
  • US11016891B2 patent drawing
  • US11016891B2 patent drawing
  • US11016891B2 patent drawing

AI summary

A computing device includes processing units and a shared processor cache. Each cache line is associated with a different plurality of accounting bits, including a unit bit associated with each processing unit. An operation by a particular processing unit on a particular cache line is identified. If the operation is a read consumed by that processing unit, and when a unit bit for that processing unit in the accounting bits associated with the particular cache line is not set, at least the value portion of the particular cache line is stored or referenced in the trace, and the particular unit bit is set. If the operation is a write, each unit bit in the accounting bits associated with the cache line that are associated with any processing unit other than the particular processing unit is cleared, and the particular unit bit associated with the particular processing unit is set.