Cache Address Conversion for Parallel Data Processing

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Solution Overview

Problem

Existing data processing systems using multiple processors face bottlenecks due to cache coherence issues and inefficiencies in parallel processing, where maintaining cache coherence increases transactions and reduces system performance, and dividing data into smaller units than cache line size prevents processors from handling parallel processing effectively.

Innovation Solution

A data processing apparatus that employs a first data processing unit to divide data into regions and process them in parallel, with an address conversion unit that adjusts data addresses based on processor cache sizes, and a second data processing unit that reads and processes the data, allowing for efficient parallel processing and maintaining cache coherence without the need for dedicated hardware.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated hardware is provided to maintain cache coherence, then cache coherence is maintained, but the number of transactions increases and system performance decreases

Engineering Contradiction:

Improvecache coherenceVSAvoidsystem performance

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the cache coherence maintenance function from dedicated hardware and implements it through software-based address conversion. The address conversion unit translates cache addresses to storage unit addresses, eliminating the need for dedicated coherence hardware while maintaining coherence through controlled address mapping.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The address conversion unit serves as an intermediary between the cache memory and storage unit. It mediates the data transfer process by converting addresses, thereby maintaining cache coherence without requiring dedicated coherence hardware or increasing transaction overhead.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If data is divided into units smaller than cache line size, then processing flexibility improves, but cache coherence maintenance becomes more complex

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidcache coherence maintenance

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the address mapping parameter by introducing a configurable address conversion mechanism. This allows the system to map cache lines to storage units in a way that accommodates data division into units smaller than cache line size while maintaining coherence through controlled address translation.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If multiple processors share common memory, then resource utilization improves, but cache coherence transactions increase

Engineering Contradiction:

Improveresource utilizationVSAvoidcache coherence transactions

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The address conversion unit performs multiple functions: it converts cache addresses to storage addresses, maintains cache coherence, and enables parallel processing. This multi-functional approach reduces the need for separate coherence maintenance mechanisms and decreases overall system complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS9256439B2Parallel processing of two-dimensional data, storage of plural data of the processing results in a cache line and transfer of the data to a memory as in the cache line

Publication Date: 2016.02.09 CANON KK

AI summary

A data processing apparatus causes multiple processors to process in parallel input data that is arrayed two-dimensionally, and stores the data of the processing results in a cache line of a cache memory, where the data of the processing results includes a plurality of pieces of data of a predetermined width that is smaller than a cache line width of the cache memory. The data stored in the cache memory is then transferred together to a main memory as in the cache line.