Programmable Cache Write Policy by Address Range for Data Coherence
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Solution Overview
Problem
The existing cache hierarchies face issues with coherence and delayed updates due to the write-back policy, where data staleness and inconsistent memory access occur across levels, and the write-through policy leads to increased memory traffic without filtering writes.
Innovation Solution
A cache system with a memory attribute register that designates memory address ranges as either write-through or write-back, allowing the cache to update all levels for write-through regions and only the first level for write-back regions, ensuring data coherence and reducing memory traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If write-back policy is used, then memory traffic is reduced, but data coherence and update timeliness deteriorate
Solution Approach 1:
The invention divides the memory address space into multiple regions, each with independently configurable cache policies (write-back or write-through). This segmentation allows different memory regions to use different write policies, enabling the system to reduce memory traffic for frequently accessed regions using write-back while maintaining data coherence for regions requiring strict consistency using write-through.
Solution Approach 2:
The invention introduces dynamic configurability of cache write policies through control registers that can be programmed to change the behavior of different memory regions. This allows the system to adapt the write policy based on runtime requirements, transitioning between write-back and write-through modes as needed to balance memory traffic and data coherence.
2Reliability
If write-through policy is used, then data coherence is maintained, but memory traffic increases
Solution Approach 1:
By segmenting the memory address space into regions with different write policies, the invention allows write-through to be applied only to specific regions where data coherence is critical, rather than globally. This reduces the overall memory traffic compared to a universal write-through policy while maintaining coherence where needed.
Solution Approach 2:
The invention applies different write policy qualities to different memory regions based on their specific requirements. Critical regions receive write-through treatment for guaranteed coherence, while non-critical regions use write-back for reduced traffic, optimizing the overall system performance.
3Loss of energy
If uniform write-back policy is used, then memory traffic is reduced, but delayed updates propagate indefinitely
Solution Approach 1:
The invention segments memory regions so that time-sensitive regions can use write-through policy to ensure immediate update propagation, while less time-sensitive regions use write-back to reduce memory traffic. This eliminates the indefinite delay problem for critical regions.
Solution Approach 2:
The configurable nature of the invention allows the system to dynamically select write-through for regions requiring timely updates and write-back for regions where delayed updates are acceptable, optimizing the trade-off between memory traffic and update propagation time.
4Adaptability or versatility
If programmable control is added, then flexibility improves, but device complexity increases
Solution Approach 1:
The control structure is segmented into multiple control registers, each managing a specific memory region's write policy. This modular approach to control complexity makes the system more manageable and easier to configure compared to a monolithic control structure.
Data Source
AI summary
This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.