Lower Level Cache Age Manipulation for Write-Back Reduction

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Solution Overview

Problem

Emerging storage class memories face challenges with slow write latency and high write frequency, which impact performance when used as DRAM replacements or in hybrid memory systems, necessitating control over the number of writes and write bandwidth.

Innovation Solution

A method and apparatus that determine whether a read request entering a lower level cache contains modified data, and if not, manipulate age information to reduce the number of write-backs to memory, distinguishing between clean and dirty cache lines to optimize eviction policies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If storage class memory is used as DRAM replacement or in hybrid memory system, then read latency is improved, but write latency increases and write frequency becomes problematic

Engineering Contradiction:
Improveread latencyVSAvoidwrite latency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system performs preliminary actions by manipulating age information of cache lines before write-back operations occur. By controlling the perceived age of clean cache lines, the system proactively prevents unnecessary write-backs to storage class memory, thereby avoiding the write latency penalty before it occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention changes the parameter of cache line age information to control eviction behavior. By manipulating age metadata rather than physical cache contents, the system alters the timing characteristics of write-back operations, effectively reducing write latency without impacting read performance.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If storage class memory is used in hybrid memory system, then memory capacity is improved, but write bandwidth requirements increase

Engineering Contradiction:
Improvememory capacityVSAvoidwrite bandwidth
Core Design Contradiction:
Quantity of substanceVSPower

Solution Approach 1:

The system extracts and identifies clean cache lines that are candidates for eviction, separating them from dirty cache lines that require write-back. By manipulating age information specifically for clean cache lines, the system removes unnecessary write operations from the memory subsystem, thereby reducing write bandwidth requirements while maintaining full memory capacity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Device complexity

If conventional cache eviction policies are used, then cache management is simplified, but number of write-backs to memory increases

Engineering Contradiction:
Improvecache managementVSAvoidnumber of write-backs
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The invention introduces age information manipulation as an intermediary mechanism between cache eviction policy and write-back operation. This intermediary layer allows the system to control write-back behavior without fundamentally changing the cache management structure, thereby reducing write-backs while maintaining relatively simple cache management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10552325B2Reducing write-backs to memory by controlling the age of cache lines in lower level cache
Publication Date: 2020.02.04 WESTERN DIGITAL TECHNOLOGIES INC
  • US10552325B2 patent drawing
  • US10552325B2 patent drawing
  • US10552325B2 patent drawing

AI summary

A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.