Cache-Aligned Adjacency Array for Graph Storage
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Solution Overview
Problem
Current compressed sparse row (CSR) representations for graph analysis applications face performance issues due to cache misses and inefficient memory access, particularly when dealing with dynamic graphs, as they require significant memory operations for insertions and deletions, and waste memory bandwidth due to non-aligned cache lines.
Innovation Solution
The proposed solution involves building an adjacency array where each element represents a vertex's neighbors, aligned to cache line lengths, eliminating the need for extra index arrays and allowing for efficient dynamic edge additions without shifting data, thereby reducing cache misses and memory waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If compressed sparse row (CSR) representation is used to store adjacency lists, then storage efficiency is improved, but memory access efficiency deteriorates due to non-aligned cache lines and cache misses
Solution Approach 1:
The patent segments the adjacency list data into fixed-size cache-line-aligned blocks. Each vertex's neighbors are stored in separately allocated cache-line-aligned memory regions, allowing independent access without causing cache line conflicts. This segmentation resolves the contradiction by maintaining compact storage while ensuring proper cache alignment for efficient access.
Solution Approach 2:
The patent introduces a new dimensional organization by creating a two-level structure: a top-level index array that maps vertices to their cache-line-aligned neighbor blocks, and the neighbor blocks themselves stored in a contiguous array. This dimensional reorganization allows the system to maintain CSR's storage efficiency while achieving cache-line alignment for optimal memory access performance.
2Quantity of substance
If CSR representation is used for graph storage, then compact storage is achieved, but dynamic graph updates require significant memory operations
Solution Approach 1:
The patent implements dynamic capabilities by allowing individual cache-line-aligned neighbor blocks to be independently allocated, modified, or deallocated. When edges are added or removed from the graph, the system can update specific vertex neighbor blocks without requiring shifts or reorganization of the entire adjacency structure, enabling efficient dynamic updates while maintaining compact storage.
Solution Approach 2:
The patent pre-allocates cache-line-aligned memory blocks for each vertex's neighbors and establishes an index mapping structure in advance. This preliminary organization allows dynamic edge additions and deletions to be performed by simply modifying pointers or individual blocks, rather than requiring complex data shifts, thus facilitating efficient dynamic graph updates.
3Device complexity
If traditional adjacency array is used, then simple structure is maintained, but cache misses increase due to non-aligned memory access
Solution Approach 1:
The patent changes the memory alignment parameter of the adjacency data structure by ensuring all neighbor blocks are allocated at cache-line boundaries. This parameter change transforms the traditional adjacency array into a cache-optimized version that maintains structural simplicity while eliminating cache misses through proper alignment, without requiring complex data structures.
Data Source
AI summary
Methods, apparatus, systems and articles of manufacture to build a storage architecture for graph data are disclosed herein. Disclosed example apparatus include a neighbor identifier to identify respective sets of neighboring vertices of a graph. The neighboring vertices included in the respective sets are adjacent to respective ones of a plurality of vertices of the graph and respective sets of neighboring vertices are represented as respective lists of neighboring vertex identifiers. The apparatus also includes an element creator to create, in a cache memory, an array of elements that are unpopulated. The array elements have lengths equal to a length of a cache line. In addition, the apparatus includes an element populater to populate the elements with neighboring vertex identifiers. Each of the elements store neighboring vertex identifiers of respective ones of the list of neighboring vertex identifiers.