Multi-Level Cache Allocation Using Half-Line Memory Fetches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The two-level memory subsystem in digital data processors experiences performance degradation due to high latency in fetching data from external memory, which affects the level two controller's busy cycles and stalls the CPU, especially when data transfer is not optimized.
Innovation Solution
The implementation includes a first-level cache with instruction and data caches, where data is fetched in half-cache lines from external memory and stored simultaneously in allocated cache lines, allowing the CPU to receive the necessary data without stalling, even as the rest of the cache line is fetched, optimizing data transfer and reducing CPU stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is fetched from external memory in full cache lines, then the cache line is completely populated, but the CPU stalls waiting for the entire cache line even if only part of it is needed
Solution Approach 1:
The cache line fetch operation is segmented into multiple smaller transactions. Instead of fetching the entire 128-byte cache line in one transaction, the system divides it into smaller chunks (e.g., 64-byte or 32-byte segments) and fetches them separately. This allows the CPU to receive and process the needed portion of data while the remaining segments are still being fetched from external memory, thereby reducing CPU stalls and improving overall fetch performance.
2Productivity
If the level two controller processes all cache allocates sequentially, then the controller remains simple, but the total time the controller is busy increases
Solution Approach 1:
The system performs preliminary actions by initiating multiple cache line fetch transactions in advance before the CPU actually needs the data. The level two controller anticipates future data requirements and starts fetching cache lines from external memory ahead of time, so that when the CPU needs the data, it is already available in the cache, reducing the controller's busy cycles and improving throughput.
Data Source
AI summary
This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.