Cache Allocation Policy for Memory Block Reuse
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Solution Overview
Problem
In memory systems, particularly with DRAM, block copy operations lead to inefficient page reuse due to random eviction streams, resulting in increased precharge and activate operations, which reduce memory utilization and efficiency.
Innovation Solution
A cache device with allocation circuitry that detects regular access patterns and alters its allocation policy to increase the likelihood of evicting data into already activated memory blocks, using regular access detection circuitry and stride detection mechanisms to manage cache lines effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional cache allocation policies are used during block copy operations, then cache operations proceed with standard allocation methods, but page reuse in memory is poor due to random eviction streams
Solution Approach 1:
The patent applies preliminary action by detecting regular access patterns in advance and proactively altering the cache allocation policy before eviction occurs. The system monitors access patterns to memory blocks and, upon detecting regularity (such as sequential or strided access), switches to an alternative allocation policy that predicts which cache lines are likely to be evicted next. This allows the system to prepare memory blocks ahead of time, reducing the need for frequent precharge and activate operations.
Solution Approach 2:
The patent implements dynamics by making the cache allocation policy adaptive and changeable based on runtime conditions. Instead of using a fixed allocation policy, the system dynamically switches between a default allocation policy and an alternative allocation policy based on the detected regularity of access patterns. This dynamic adaptation allows the cache to optimize its behavior for different workload characteristics, improving memory utilization when regular patterns are detected while maintaining standard operation during irregular access.
2Ease of operation
If cache allocation is performed using random or pseudo-random schemes, then cache line eviction appears random, but this creates poor correlation between read and write eviction streams
Solution Approach 1:
The patent applies feedback by monitoring access patterns to memory blocks and using this information to adjust the cache allocation policy. The system continuously observes whether access patterns exhibit regularity (such as sequential or strided access) and feeds this information back to the allocation circuitry, which then switches between default and alternative allocation policies accordingly. This feedback mechanism allows the system to adapt to workload characteristics and improve memory interface utilization without complex predetermined schemes.
Solution Approach 2:
The patent implements parameter changes by altering the cache allocation policy parameters based on detected access pattern regularity. When regular access patterns are detected, the system changes the allocation policy from a default scheme to an alternative scheme that is optimized for regular patterns. This parameter change enables the cache to better predict and correlate eviction streams, improving memory interface bus utilization while maintaining ease of operation through automated detection and switching.
3Quantity of substance
If the number of open pages in memory is limited, then memory resources are constrained, but closing pages to open new ones reduces efficiency
Solution Approach 1:
The patent applies preliminary action by predicting which cache lines will be evicted based on detected regular access patterns and proactively managing cache allocation accordingly. By identifying regular patterns such as sequential or strided access early in the block copy operation, the system can allocate cache lines in a way that maintains better correlation between read and write eviction streams. This preliminary detection and adaptation allows the system to maximize page reuse within the limited number of open pages, improving block copy operation efficiency without requiring additional page openings.
Data Source
AI summary
A cache device is provided for use in a data processing apparatus to store data values for access by an associated master device. Each data value has an associated memory location in a memory device, and the memory device is arranged as a plurality of blocks of memory locations, with each block having to be activated before any data value stored in that block can be accessed. The cache device comprises regular access detection circuitry for detecting occurrence of a sequence of accesses to data values whose associated memory locations follow a regular pattern. Upon detection of such an occurrence of a sequence of accesses by the regular access detection circuitry, an allocation policy employed by the cache to determine a selected cache line into which to store a data value is altered with the aim of increasing a likelihood that when an evicted data value output by the cache is subsequently written to the memory device, the associated memory location resides within an already activated block of memory locations. Hence, by detecting regular access patterns, and altering the allocation policy on detection of such patterns, this enables a reuse of already activated blocks within the memory device, thereby significantly improving memory utilization, thereby giving rise to both performance improvements and power consumption reductions.