Cache Appliance Perfect Hashing for Packet Pattern Matching
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Solution Overview
Problem
Conventional Network Attached Storage (NAS) devices face performance limitations due to high CPU cycle consumption for processing and searching data packets, leading to suboptimal disk storage access times and network packet processing, especially in large communication networks with numerous connections.
Innovation Solution
A high-performance, scalable standalone cache appliance employing a perfect hashing memory scheme to rapidly inspect incoming packets for predetermined patterns, using a data structure pointer and index offset to quickly locate matching patterns in memory, thereby reducing the need for extensive searches and optimizing cache operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional NAS devices use traditional packet inspection methods to search for patterns in incoming data packets, then they can identify predetermined patterns to implement caching policies, but they consume excessive CPU cycles (up to 85% for pattern matching and content inspection) and suffer from slow disk storage access times
Solution Approach 1:
The patent segments the packet inspection process into distinct functional modules: a pattern detection module that identifies predetermined patterns in packet payloads, and a separate caching policy module that uses these detected patterns to make caching decisions. This segmentation allows the CPU to offload pattern matching to specialized hardware or optimized routines, reducing overall CPU cycle consumption while maintaining inspection effectiveness.
Solution Approach 2:
The patent implements preliminary pattern detection and classification before full packet processing. By identifying predetermined patterns early in the packet inspection process, the system can make rapid caching decisions without performing exhaustive content analysis on every packet, thereby reducing CPU cycle consumption while maintaining high packet processing throughput.
2Speed
If NAS devices increase cache memory size to improve access response time, then cache hit rates may improve, but hardware costs, chip size, and power consumption increase significantly
Solution Approach 1:
The patent changes the parameters used for cache decision-making from traditional methods (such as simple LRU based on access time) to pattern-based parameters. By detecting predetermined patterns in packet payloads and using these patterns as the basis for caching decisions, the system achieves high cache hit rates with smaller cache memory sizes, thereby improving access response time without proportionally increasing hardware resources.
3Measurement precision
If conventional systems perform extensive searches of large connection tables (e.g., 3 GB file with 1 M connections) to inspect incoming packets, then they can accurately determine packet routing, but the search process is time-consuming and reduces network packet processing speed
Solution Approach 1:
The patent creates compact copies or representations of connection information based on detected patterns, rather than searching the entire large connection table for every packet. By maintaining pattern-based indexes or hash tables that map predetermined patterns to connection information, the system achieves accurate packet inspection with significantly reduced search time, thereby improving packet processing speed while maintaining inspection accuracy.
Data Source
AI summary
A method, system and program are disclosed for accelerating data storage in a cache appliance that transparently monitors NFS and CIFS traffic between clients and NAS subsystems and caches files in a cache memory by using a perfect hashing memory index technique to rapidly detect predetermined patterns in received packet payloads and retrieve matching patterns from memory by generating a data structure pointer and index offset to directly address the pattern in the datagram memory, thereby accelerating evaluation of the packet with the matching pattern by the host processor.