Cache Architecture Generation from High-Level Language Descriptions
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Solution Overview
Problem
Software engineers face a daunting task in transitioning from a microprocessor programming model to a data streaming model to generate configuration bitstreams for FPGAs, requiring an in-depth understanding of circuit operations and involving substantial conversion of high-level language source code.
Innovation Solution
A method for generating cache architecture from high-level language descriptions, allowing for the identification and assignment of memory accesses without data dependencies to a distributed cache, enabling direct compilation of microprocessor memory model code for FPGAs without converting it to a data streaming model.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software engineers transition from microprocessor programming model to data streaming model for FPGA implementation, then system performance and parallelism are improved, but programming complexity and conversion effort increase significantly
Solution Approach 1:
The patent introduces a compiler as an intermediary tool that automatically translates high-level language source code written in microprocessor programming model into FPGA configuration bitstreams in data streaming model. This mediator handles the complex conversion process, shielding software engineers from the complexity of data streaming model while enabling FPGA parallelism and performance benefits.
Solution Approach 2:
The system enables software engineers to write code in their preferred microprocessor programming model without manual conversion, allowing the compilation process to automatically optimize and transform the code for FPGA execution. This self-service approach maintains ease of programming while achieving hardware acceleration benefits.
2Manufacturing precision
If high-level language source code is manually converted to data streaming model, then FPGA implementation accuracy is improved, but time consumption and conversion effort increase
Solution Approach 1:
The compiler performs preliminary analysis and transformation of high-level language source code, identifying memory access patterns and data dependencies before generating FPGA configuration. This preliminary processing ensures accurate FPGA implementation while automating the time-consuming conversion process that would otherwise require manual effort.
Solution Approach 2:
The patent replaces the mechanical manual conversion process with an automated compiler system that uses algorithms and heuristics to transform code. This substitution eliminates manual labor and reduces conversion time while maintaining or improving implementation accuracy through systematic analysis.
3Productivity
If memory accesses without data dependencies are assigned to distributed cache, then memory bottlenecks are reduced and parallelism is improved, but cache architecture complexity increases
Solution Approach 1:
The patent segments memory access operations into different categories based on data dependency analysis. Memory accesses without data dependencies are assigned to distributed cache structures, while dependent accesses follow traditional memory paths. This segmentation enables parallel execution of independent operations while managing cache complexity through structured organization.
Solution Approach 2:
The system applies different quality characteristics to different parts of the memory system. Distributed cache structures are implemented locally at specific processing elements where they can exploit data locality, while maintaining global memory coherence through coordinated access protocols. This local optimization improves parallelism without requiring system-wide cache complexity.
Data Source
AI summary
Generation of cache architecture from a high-level language description is described. A description of an application in a high-level programming language is obtained. A data flow representation is generated from the description suitable for providing an implementation in hardware. The generating includes: identifying accesses to memory associated with the description; determining that at least a portion of the accesses to memory do not have one or more data dependencies for locally cacheable data; and assigning the portion to a distributed cache.