Cache-Aware Low-Power Memory During Active Processor States
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Solution Overview
Problem
Existing architectures hinder the opportunity for memory to enter a low power state during processor idle conditions due to the requirement of maintaining access to memory during non-idle processor states.
Innovation Solution
Instructing a first processing component to avoid accessing the cache and a second processing component to allocate in the cache, while using an activity buffer to temporarily idle the memory, allowing the memory to enter a low power state even during active processor states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor enters a low power state, then power consumption is reduced, but the memory cannot enter a low power state because the processor may need to access it
Solution Approach 1:
The system segments the processor into multiple independent processing components (first processing component and second processing component) that can operate independently. This allows one component to be idle while another remains active, enabling the memory to enter low power state during partial idle periods without requiring the entire processor to be idle.
Solution Approach 2:
The system implements periodic action by allowing the memory to enter low power state during periodic idle windows between memory accesses from different processing components. The memory alternates between active and low power states based on the periodic activity patterns of the processing components.
2Loss of energy
If the memory enters a low power state, then memory power consumption is reduced, but this requires the processor to be idle which reduces productivity
Solution Approach 1:
By dividing the processor into multiple independent processing components, the system eliminates the requirement for complete processor idle time. While one component processes data from the memory, another component can be idle, allowing the memory to enter low power state without reducing overall processor productivity.
Solution Approach 2:
The system uses preliminary action by pre-fetching data into buffers before the memory needs to enter low power state. This allows the memory to be idle long enough to enter low power state while the buffers contain sufficient data to keep processing components productive during the memory's low power period.
3Productivity
If multiple processing components access the memory simultaneously, then processor productivity is maintained, but the memory cannot enter a low power state
Solution Approach 1:
The system segments memory access patterns by assigning different processing components to different buffers or memory regions. This segmentation allows the memory to serve one component while another component's buffer is being processed, creating opportunities for the memory to enter low power state during transitions between components.
Solution Approach 2:
The system introduces buffers as intermediary structures between the memory and processing components. These buffers act as mediators that decouple the memory from continuous processing demands, allowing the memory to enter low power state while data is being processed from the buffers by the processing components.
Data Source
AI summary
The disclosed device includes multiple processing component, and a cache. One of the processing components can be instructed to avoid allocating to the cache and another of the processing components can be allowed use the cache while reducing accessing a memory. The memory can then enter a low power state in response to an idle state of the memory from the processing components avoiding accessing the memory for a period of time. Various other methods, systems, and computer-readable media are also disclosed.