Cache-Aware Low Power Mode Control for Multi-Core SoCs
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Solution Overview
Problem
Modern portable computing devices face challenges in managing low power modes for cores/CPUs due to fixed and unchanging decision algorithms that do not consider the current operating state of the cores and associated cache memories, leading to inefficient battery life.
Innovation Solution
Implement a dynamic system that considers the operating state of the cache memory to make informed decisions about entering low power modes for cores/CPUs, using access counters to record cache activity and a low power mode controller to determine the best power-saving strategies based on cache activity levels and exit latencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a core is placed in low power mode to reduce energy consumption, then power savings are achieved, but the time and energy overhead for reactivating the core increases
Solution Approach 1:
The patent applies dynamics by making the low power mode decision adaptive rather than static. The system dynamically evaluates cache activity levels and exit latencies to determine whether entering low power mode is beneficial, allowing the decision criteria to change based on real-time system state rather than using fixed thresholds
Solution Approach 2:
The system performs preliminary action by evaluating cache activity levels and calculating exit latencies before making the low power mode decision. This advance assessment of the reactivation cost allows the system to predict whether the core should enter low power mode, preventing unnecessary transitions that would waste time and energy
2Device complexity
If fixed decision algorithms are used for low power mode transitions, then implementation simplicity is maintained, but adaptability to current operating state is reduced
Solution Approach 1:
The patent implements feedback by continuously monitoring cache activity levels and using this information to adjust low power mode decisions. The system feeds back the actual cache state and exit latency measurements to the decision algorithm, enabling adaptive behavior that responds to changing operating conditions while maintaining a manageable level of complexity
Solution Approach 2:
The system applies parameter changes by modifying the decision criteria based on measured cache activity levels and exit latencies. Rather than using fixed thresholds, the algorithm adjusts its parameters dynamically according to the observed system state, improving adaptability without requiring complete redesign of the decision logic
Data Source
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AI summary
Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A core of the multi-core SoC entering an idle state is identified. For a low power mode of the core, an entry power cost of the core and an exit power cost of the core is calculated. A working set size for a cache associated with the core is also calculated. A latency for the cache to exit the low power mode of the core is calculated using the working set size. Finally, a determination is made whether the low power mode for the core results in a power savings over an active mode for the core based in part on the entry and exit power costs of the core, and the latency of the cache exiting the low power mode.