Cache Bank Power-Down via Locality-Based Line Migration

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Solution Overview

Problem

Current power management systems face challenges in efficiently transitioning cache memory banks to low-power mode due to high transition latency, which reduces the effectiveness of power management and the frequency of transitions, despite notifications for power-down operations.

Innovation Solution

A computing system with a cache array and controller that partitions cache memory into banks and subdivisions, allowing selective migration or write-back of cache lines based on locality estimation and criteria such as LRU values and shared status across processor cores, to optimize power-down operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all cache blocks are migrated or evicted before transitioning to low-power mode, then data integrity is maintained, but transition latency becomes too large

Engineering Contradiction:
Improvedata integrityVSAvoidtransition latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The cache array is divided into multiple independent banks, each capable of being powered down separately. This segmentation allows the system to transition individual banks to low-power mode without requiring migration of all cache blocks across the entire cache, thereby reducing transition latency while maintaining data integrity for the powered-down bank.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of migrating or evicting all cache blocks before power-down, the system performs partial action by only migrating or evicting a subset of cache blocks from the specific bank being powered down. This partial action reduces the time required for transition while still preserving data integrity for the blocks that remain in the powered-down bank.

Inventive Principle:
Principle #16Partial or excessive action

2Use of energy by moving object

If cache banks are powered down frequently to reduce power consumption, then energy savings increase, but transition overhead increases

Engineering Contradiction:
Improvepower consumptionVSAvoidtransition overhead
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

By segmenting the cache into multiple independently controllable banks, the system can power down only the specific banks that are not currently in use, rather than powering down the entire cache. This selective approach reduces the transition overhead associated with frequent power-down operations while still achieving significant energy savings for the inactive banks.

Inventive Principle:
Principle #1Segmentation

3Productivity

If cache capacity and associativity limits are enforced, then cache performance is maintained, but flexibility in managing cache blocks with specific properties is reduced

Engineering Contradiction:
Improvecache performanceVSAvoidflexibility in managing cache blocks
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The cache is segmented into multiple banks, and within each bank, cache sets are organized to provide finer-grained control over cache blocks with specific properties. This segmentation allows the system to enforce capacity and associativity limits at the bank level while providing flexibility to manage specific cache blocks through targeted migration or eviction operations within individual banks.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9251081B2Management of caches
Publication Date: 2016.02.02 ADVANCED MICRO DEVICES INC
  • US9251081B2 patent drawing
  • US9251081B2 patent drawing
  • US9251081B2 patent drawing

AI summary

A system and method for efficiently powering down banks in a cache memory for reducing power consumption. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, each comprising multiple cache sets. In response to a request to power down a first bank of the multiple banks in the cache array, the cache controller selects a cache line of a given type in the first bank and determines whether a respective locality of reference for the selected cache line exceeds a threshold. If the threshold is exceeded, then the selected cache line is migrated to a second bank in the cache array. If the threshold is not exceeded, then the selected cache line is written back to lower-level memory.