Cache Bank Spreading for Compressed Data Access
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Solution Overview
Problem
The mismatch between compressed data block sizes and cache line sizes in cache memory leads to irregular use of cache resources, resulting in uneven distribution of compressed data across cache banks, as cleared address bits limit bank selection options.
Innovation Solution
Implementing cache bank spreading by applying arithmetic or operational functions to conserved address bits to recreate and reinstate cleared bank select bits, ensuring more frequent distribution of compressed data across cache banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data compression is applied to reduce data size, then storage efficiency is improved, but cache bank utilization becomes uneven
Solution Approach 1:
The patent changes the parameter of address bit usage by reinstating cleared address bits through arithmetic operations. When data is compressed, certain address bits are cleared (e.g., bits 0-7 for 256-byte to 128-byte compression), but the patent reapplies these bits using XOR operations with other address bits to restore bank selection capability, thereby maintaining uniform cache bank utilization while preserving compression benefits
Solution Approach 2:
The patent introduces an intermediary mechanism (arithmetic operation unit) that processes address bits between the compression unit and cache memory. This intermediary reinstates the cleared address bits by performing XOR operations, acting as a mediator that resolves the conflict between compressed data size and cache bank distribution
2Quantity of substance
If compressed data block sizes are used, then storage capacity is improved, but access efficiency deteriorates due to irregular cache resource use
Solution Approach 1:
The patent modifies address parameters by reinstating cleared bits through arithmetic operations, transforming the address structure to enable uniform cache bank access patterns while maintaining the space-efficient compressed data blocks
3Quantity of substance
If address bits are cleared during compression, then data size is reduced, but cache bank selection capability is lost
Solution Approach 1:
The patent applies parameter transformation by using arithmetic operations (XOR) to regenerate the functionality of cleared address bits from remaining address bits, restoring cache bank selection capability without increasing data size
Solution Approach 2:
The patent creates a copy of the address bit selection functionality by deriving reinstated bits from XOR operations on other address bits, effectively copying the bank selection capability from available bits rather than relying on the original cleared bits
Data Source
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Figure 3B
AI summary
Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.