Cache-Based Read Command Selection for NVDIMM-P Memory Subsystems

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Solution Overview

Problem

Existing memory sub-systems using non-deterministic memory protocols, such as NVDIMM-P, face inefficiencies in read commands as they often result in non-deterministic response times due to cache hits and misses, leading to performance bottlenecks and opportunity costs in data transfer.

Innovation Solution

A host system selectively sends cache-based read commands to a memory sub-system based on a history of past commands, utilizing a content addressable memory (CAM) to determine the likelihood of cache hits, thereby optimizing read performance by choosing between SREAD and XREAD commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a cache-based read command (SREAD) is sent to the memory sub-system, then read speed is improved when data is cached, but response time becomes non-deterministic due to cache hits and misses

Engineering Contradiction:
Improveread speedVSAvoidresponse time determinism
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The host system performs preliminary actions by tracking the history of past read commands and predicting future cache states before issuing read commands. This allows the host to proactively choose between SREAD and XREAD commands based on predicted cache hits or misses, thereby preparing for deterministic response times in advance rather than reacting to non-deterministic cache behavior after the fact.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If a cache-based read command is used, then data transfer efficiency is improved on cache hits, but opportunity costs increase due to unnecessary responses during cache misses

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidopportunity cost
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The host system implements feedback mechanisms by continuously monitoring and tracking the history of past read commands and their outcomes (cache hits or misses). This feedback information is used to predict future cache states and adjust command selection accordingly, creating a closed-loop system that optimizes data transfer efficiency while minimizing opportunity costs through informed decision-making.

Inventive Principle:
Principle #23Feedback

3Productivity

If the host system tracks history of past commands to predict cache states, then read performance is optimized, but device complexity increases due to additional tracking mechanisms

Engineering Contradiction:
Improveread performanceVSAvoidtracking mechanism complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The host system applies segmentation by dividing the tracking mechanism into modular components that monitor specific aspects of command history independently. This modular approach allows the system to track cache state predictions without creating a monolithic complex structure, making the tracking mechanism more manageable and easier to implement while still achieving optimized read performance.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11698756B2Cache-based memory read commands
Publication Date: 2023.07.11 MICRON TECHNOLOGY INC
  • US11698756B2 patent drawing
  • US11698756B2 patent drawing
  • US11698756B2 patent drawing

AI summary

Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.