Cache Block Batching for DRAM Page Access Optimization
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Solution Overview
Problem
Current cache memory management systems do not effectively utilize data access frequency to optimize access time for frequently accessed data, leading to inefficiencies in data transfer between cache and memory.
Innovation Solution
Implement a method where data is stored in a cache with a block set coupled to a buffer, evicting blocks based on priority status and recentness of use, and assigning priority status to blocks with dirty values when the page block count exceeds a threshold, with priority status removed when the count falls below a second threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data is stored in cache with standard eviction policies, then cache capacity is maintained, but access time for frequently accessed data is not optimized
Solution Approach 1:
The patent changes the parameter of block eviction by introducing a new criterion: the number of dirty blocks sharing the same memory page. Instead of using traditional LRU or random eviction, the system evicts blocks whose corresponding memory page has fewer than a threshold number of dirty blocks (e.g., less than 2), thereby prioritizing retention of blocks belonging to frequently accessed memory pages.
Solution Approach 2:
The patent performs preliminary action by counting the number of dirty blocks for each memory page before eviction decisions are made. This pre-computed information is used to guide eviction choices, allowing the system to proactively retain blocks that are likely to be needed soon based on their memory page's dirty block count, rather than reacting to cache misses.
2Loss of energy
If cache eviction is based on traditional LRU policy, then implementation is simple, but data locality and energy consumption are not optimized
Solution Approach 1:
The patent changes the eviction parameter from time-based (LRU) to access frequency-based (dirty block count per page). By using the number of dirty blocks as a proxy for data locality and access frequency, the system optimizes energy consumption by keeping frequently accessed data in cache, reducing the need for expensive memory accesses.
Solution Approach 2:
The system uses information already available in the cache management structure (dirty bit and page mapping) to make eviction decisions. The dirty block count per page is naturally tracked as part of normal cache operation, and this existing information is repurposed to guide eviction without requiring additional complex monitoring or metadata structures.
3Loss of time
If all cache blocks are treated equally, then management is straightforward, but access time for frequently accessed data cannot be improved
Solution Approach 1:
The patent applies local quality by treating different cache blocks differently based on their memory page's dirty block count. Instead of uniform treatment, blocks belonging to pages with low dirty block counts are prioritized for eviction, while blocks from pages with high dirty block counts are retained. This localized differentiation based on memory page characteristics optimizes access time for frequently accessed data.
Data Source
AI summary
To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.