Cache Bit Inversion Tracking for Low-Power MRAM Writes
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Solution Overview
Problem
MRAM write operations consume more power compared to SRAM due to higher current requirements, and conventional MRAM systems employ read-modify-write schemes that incur additional power consumption and slower performance by necessitating read and modify operations for every write operation.
Innovation Solution
Implementing data bit inversion tracking in cache memory to reduce the number of bits written during write operations by comparing current and new data words and storing a bit change track word, allowing data to be written in either inverted or non-inverted form, thereby minimizing the number of write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If MRAM write operations use conventional approaches, then data can be written to memory, but power consumption increases due to higher current requirements
Solution Approach 1:
The patent segments the write operation into two parts: (1) a read operation to retrieve current data, and (2) a modify operation that only writes changed bits. This segmentation allows the system to avoid writing all bits during every write operation, thereby reducing power consumption while maintaining data integrity and write reliability.
Solution Approach 2:
The patent implements partial action by only writing the bits that have changed between the current data and new data, rather than writing all bits. The write operation performs a bitwise comparison and only programs the MTJs for bits that differ, reducing the total current required while ensuring complete data update reliability.
2Use of energy by moving object
If read-modify-write schemes are employed to reduce write bits, then power consumption decreases, but performance deteriorates due to additional read and modify operations
Solution Approach 1:
The patent merges the read operation and modify operation into a single integrated process. The read operation retrieves current data, and the modify operation simultaneously compares and writes only changed bits in one continuous flow, eliminating the performance penalty of sequential operations while maintaining power savings.
Solution Approach 2:
The patent performs preliminary action by pre-computing the bitwise XOR operation between current and new data to identify changed bits before initiating the write operation. This preliminary identification allows the system to prepare the minimal set of bits to be written, optimizing both power consumption and operation speed by avoiding unnecessary write cycles.
3Reliability
If all bits are written during write operations, then data integrity is ensured, but the number of write operations increases leading to higher power consumption
Solution Approach 1:
The patent implements feedback by using the result of the bitwise XOR operation to determine which bits actually need to be written. The system feedbacks this information to control the write operation, ensuring that only necessary bits are programmed. This maintains data integrity through complete verification while minimizing the number of write operations and associated power consumption.
Solution Approach 2:
The patent changes the parameter of write operation granularity from word-level (all bits) to bit-level (only changed bits). By dynamically adjusting the write scope based on the actual data changes detected through XOR comparison, the system ensures data integrity for all bits while reducing power consumption by limiting physical write operations to only those bits that require updating.
Data Source
AI summary
Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.