Cache Memory Access via Bit Prediction Unit
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Solution Overview
Problem
Traditional cache accessing structures in CPUs are inefficient due to the need for physical address generation before cache access, which decreases cache memory efficiency and is unsuitable for large cache capacities.
Innovation Solution
A method and device that use a bit prediction unit to generate prediction bits for virtual addresses, allowing the load/store unit to create a predicted cache index for direct cache access, enabling simultaneous cache access and address translation without waiting for physical address generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional cache accessing structure is used with physical address generation before cache access, then address translation is completed accurately, but cache access efficiency decreases and large cache capacity becomes unsuitable
Solution Approach 1:
The patent applies preliminary action by predicting the cache index before the physical address is fully generated. The bit prediction unit predicts the cache index based on the virtual address and page offset before the MMU completes address translation, allowing the cache to be accessed in advance without waiting for the complete physical address. This resolves the contradiction by enabling early cache access (improving productivity) while maintaining accurate address translation through subsequent verification.
Solution Approach 2:
The patent introduces a bit prediction unit as an intermediary between the virtual address and the cache access process. This intermediary component predicts the cache index using the virtual address and page offset, serving as a mediator that allows cache access to proceed before the final physical address is ready. This resolves the contradiction by enabling efficient cache access through prediction while the MMU continues address translation in the background.
2Reliability
If cache access waits for physical address generation, then address translation accuracy is ensured, but cache access time increases
Solution Approach 1:
The patent applies preliminary action by performing cache index prediction before the physical address is fully generated. The bit prediction unit calculates the predicted cache index based on the virtual address and page offset in advance, allowing the cache access to start before the MMU completes address translation. This resolves the contradiction by reducing cache access time through early access while maintaining translation accuracy through subsequent verification of the predicted index.
Solution Approach 2:
The patent implements continuity of useful action by overlapping the cache access operation with the address translation operation. While the MMU is translating the virtual address to physical address, the LSU is simultaneously accessing the cache using the predicted index. This parallel execution ensures that both address translation accuracy and cache access speed are maintained without waiting for one operation to complete before starting the other.
3Productivity
If modified cache accessing structure with simultaneous access is used, then cache access efficiency improves, but maximum cache memory size is limited
Solution Approach 1:
The patent applies preliminary action by predicting the cache index before the physical address is fully generated. This allows the system to access the cache using virtual address information (page offset) combined with predicted bits, enabling the cache to be accessed in parallel with address translation. This resolves the contradiction by maintaining high cache access efficiency through simultaneous operations while removing the limitation on maximum cache size by using prediction-based indexing rather than requiring complete physical address translation first.
Data Source
AI summary
A method and a device for accessing a cache memory are provided. The method comprises: generating, by a bit prediction unit (BPU), a prediction bit corresponding to an instruction instructing to access the cache memory from a central processing unit (CPU); generating, by an instruction execution unit (IEU), a virtual address corresponding to the instruction; generating, by a load/store unit (LSU), a predicted cache index according to the prediction bit and a part of a virtual page offset of the virtual address; and reading, by the LSU, data from the cache memory by using the predicted cache index. Therefore, the maximum size of the cache memory could be increased.