Digital Power Multiplexer for Cache Bitcell Voltage Selection
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Solution Overview
Problem
Modern computing systems face challenges in efficiently routing and managing power supply voltages to processor cores and associated cache memories, particularly when different cores operate at different performance levels and voltages, leading to complex routing and potential issues like reverse level shifting and direct current paths between supply voltages.
Innovation Solution
Implementing an integrated digital power multiplexer that selectively switches between fixed and variable power voltages to ensure cache bitcell arrays operate at a minimum safe voltage while preventing reverse level shifting, using transistors and level shifters to manage power distribution based on overdrive signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple power voltages are routed to processor cores and cache memory to support different performance levels, then adaptability is improved, but device complexity increases
Solution Approach 1:
The power multiplexer is designed to handle multiple power voltage inputs (VDDCORE1, VDDCORE2, VDDCEMIN) and selectively route the appropriate voltage to the cache bitcell array based on operating conditions. This multi-functional device replaces what would otherwise require multiple dedicated power routing paths, reducing overall system complexity while maintaining adaptability to different performance levels
Solution Approach 2:
The power multiplexer dynamically selects between different power voltage sources based on real-time operating conditions and overdrive signals. This dynamic switching capability allows the system to adapt power delivery to match current performance requirements without requiring static, complex routing for all possible voltage combinations
2Use of energy by moving object
If power switching is implemented to manage different voltages, then power management efficiency is improved, but device complexity increases
Solution Approach 1:
The power multiplexer acts as an intermediary device between multiple power voltage sources and the cache bitcell array. It mediates the power delivery by selectively connecting the appropriate voltage source, thereby improving power management efficiency without requiring complex control logic in the core or cache structures themselves
Solution Approach 2:
The power multiplexer combines multiple power voltage input paths into a single unified output path that serves the cache bitcell array. This merging approach consolidates what would otherwise require separate power management circuits for each voltage source, improving efficiency while limiting the increase in device complexity
3Reliability
If reverse level shifting is prevented by voltage selection, then reliability is improved, but device complexity increases
Solution Approach 1:
The power multiplexer performs preliminary voltage selection before power is delivered to the cache bitcell array. By pre-selecting the appropriate voltage level based on operating conditions and overdrive signals, the system prevents reverse level shifting issues from occurring in the first place, improving reliability without requiring complex correction circuits
Solution Approach 2:
The power multiplexer uses overdrive input signals and voltage level detection to determine the appropriate power voltage to supply. This feedback mechanism ensures that the cache receives the correct voltage level under all operating conditions, preventing reverse level shifting and improving overall system reliability
Data Source
AI summary
A memory instance comprises a bitcell array and peripheral circuitry. A bitcell array power supply provides a fixed voltage for the bitcell array, and a peripheral logic power supply provides a variable voltage for peripheral circuitry. A digital power multiplexer is operable to provide a higher of the bitcell array power supply fixed voltage and the peripheral logic power supply variable voltage to the bitcell array.