Cache Block Architecture for Multi-Bank Flash Programming
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Solution Overview
Problem
Multilevel flash memory devices face inefficiencies in programming speed due to large program units, which hinder the management of file systems and require a method to enhance speed while maintaining smaller program units.
Innovation Solution
A nonvolatile semiconductor memory device incorporates a memory cell array with cache blocks and page buffers, allowing page data to be loaded and programmed into cache blocks for the majority of banks, with the last bank's data being loaded and programmed simultaneously, utilizing a high-performance programming command to reduce overall programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If page data is programmed into each bank sequentially, then the program unit size remains small and manageable, but the overall programming time increases
Solution Approach 1:
The patent introduces cache blocks within each bank to temporarily store page data before final programming. This preliminary storage action allows data to be prepared in advance, enabling parallel programming operations across multiple banks without increasing the effective program unit size, thus reducing total programming time.
Solution Approach 2:
The patent divides each bank into cache blocks, creating a hierarchical structure where data is first loaded into smaller cache blocks and then programmed into the bank. This segmentation allows for more granular control of the programming process and enables parallel operations without requiring large program units.
2Productivity
If multiple banks are programmed simultaneously, then programming speed increases, but the management of file systems becomes more difficult
Solution Approach 1:
By dividing banks into cache blocks and using a staged programming approach, the patent maintains smaller, more manageable data units that are easier to track and manage in file systems, while still enabling parallel programming operations across multiple banks to improve speed.
3Device complexity
If page data is loaded into page buffer and immediately programmed, then the programming process is simple, but the programming time per page is large
Solution Approach 1:
The patent introduces cache blocks as an intermediate storage stage between the page buffer and the bank. Data is first loaded into the page buffer, then transferred to cache blocks for preliminary processing and organization, and finally programmed into the bank. This preliminary action in cache blocks enables more efficient programming operations and reduces the time per page.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.