Cache Blocking State Machine for Store-Conditional Protection
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Solution Overview
Problem
In shared memory multiprocessor systems, existing methods for synchronizing access to data in shared memory, such as load-reserve and store-conditional instructions, face challenges in maintaining efficient data coherence and reducing traffic volume on the interconnect fabric as system size increases, leading to increased access latencies and bandwidth requirements.
Innovation Solution
The implementation of multiple coherency domains within the data processing system, where each domain is formed by a collection of processing units, reduces inter-domain broadcast communication by allowing memory access requests to be serviced with participation from fewer domains, and the use of a blocking state machine in the cache to extend protection windows for store-conditional requests, thereby increasing the likelihood of successful updates without obtaining the target cache line from another processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If load-reserve and store-conditional instructions are used to synchronize access to shared memory, then data coherence is maintained, but access latency increases and interconnect traffic volume increases
Solution Approach 1:
The system segments the shared memory access space into multiple coherency domains. Each domain is identified by a domain ID that is compared against the snooped address during cache snooping operations. This segmentation allows the cache to selectively apply coherence protocols only within relevant domains, reducing unnecessary broadcast communication and interconnect traffic while maintaining data coherence for accessed memory regions.
Solution Approach 2:
The cache implements domain-specific coherence handling by comparing the domain ID of snooped addresses with the domain ID of protected addresses. This local quality approach enables the cache to apply protection window extensions and coherence protocols selectively to specific domains rather than universally, reducing overall system traffic and access latency while maintaining coherence where needed.
2Reliability
If protection window extension is applied to store-conditional requests, then successful update likelihood increases, but system traffic and bandwidth requirements increase
Solution Approach 1:
The protection window extension is segmented by coherency domain boundaries. When a store-conditional request succeeds, the cache extends protection only for addresses within the same coherency domain (matching domain ID), rather than extending protection system-wide. This domain-limited protection extension increases successful update likelihood for local operations while preventing unnecessary traffic generation across the entire interconnect fabric.
3Quantity of substance
If broadcast communication is reduced by implementing coherency domains, then interconnect traffic decreases, but data coherence maintenance becomes more complex
Solution Approach 1:
The system performs preliminary domain ID comparison before executing full coherence protocols. During cache snooping operations, the domain ID of the snooped address is compared against the domain ID of protected addresses in advance. This preliminary action filters out unrelated domains early in the process, reducing interconnect traffic while maintaining coherence for relevant domains without requiring complex post-processing.
Solution Approach 2:
The cache implements self-service coherence management by autonomously comparing domain IDs and determining whether protection window extensions should be applied. The cache independently evaluates domain matches and applies or withholds protection extensions without requiring complex external coordination, simplifying coherence management while reducing traffic through selective domain-based filtering.
Data Source
AI summary
A processing unit includes a processor core that executes a store-conditional instruction that generates a store-conditional request specifying a store target address. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The cache includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request snooped on a system interconnect during a protection window extension following servicing of the store-conditional request. The cache is configured to vary a duration of the protection window extension for different snooped memory access requests based on one of broadcast scopes and the relative locations of masters of the snooped memory access requests.