Cache Buffer Selector for Cross-Group Data Repair in Semiconductor Memory
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Solution Overview
Problem
Existing semiconductor memory devices face limitations in performing flexible repair operations due to the lack of efficient data transfer mechanisms between different memory areas, leading to challenges in maintaining data integrity and reliability during repair processes.
Innovation Solution
A cache buffer system is introduced, comprising a selector and an I/O controller that enables normal and cross repair operations by transferring data between different cache groups, allowing for flexible data management and repair within the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a traditional cache buffer structure is used, then the device complexity is low, but the repair operation flexibility is insufficient
Solution Approach 1:
The cache buffer structure dynamically reconfigures data transfer paths between cache groups based on repair needs. The selector circuit switches between normal operation mode (first data line to first cache group, second data line to second cache group) and cross repair mode (first data line to second cache group, second data line to first cache group), enabling flexible repair operations without permanent structural changes
Solution Approach 2:
The cache buffer is designed to perform multiple functions: normal data caching, normal repair operations within the same cache group, and cross repair operations between different cache groups. The same data lines and cache groups serve both normal operation and repair functions, eliminating the need for separate dedicated repair structures
2Reliability
If data transfer between cache groups is restricted, then the device complexity is low, but the data integrity during repair operations deteriorates
Solution Approach 1:
The selector circuit acts as an intermediary that controls and manages data transfer between cache groups. It selectively connects data lines to appropriate cache groups based on operation mode, enabling safe cross-group data transfer for repair operations while preventing unauthorized or erroneous transfers during normal operation, thus ensuring data integrity
3Adaptability or versatility
If normal repair operation is performed, then the manufacturing precision is maintained, but the repair coverage is limited to specific cache groups
Solution Approach 1:
The system uses control signals from the I/O controller to feedback the operational mode to the selector. Based on this feedback, the selector appropriately routes data lines to cache groups, ensuring that cross repair operations are performed only when intended and that normal operation data paths remain unchanged, thus maintaining data transfer accuracy while expanding repair coverage
Data Source
AI summary
A cache buffer coupled to a page buffer includes: a first cache group and a second cache group corresponding to a first area and a second area of a memory cell array; a selector coupled to the first and second cache groups; and an input/output (I/O) controller coupled to the selector and configured to output data to the first and second cache groups or receive data input from the first and second cache groups. The selector: performs normal repair operation by transferring data received through a first data line to the first cache group and transferring data received through a second data line to the second cache group; performs cross repair operation by transferring data received through the first data line to the second cache group and transferring data received through the second data line to the first cache group.