Cache Bypass via Binary Tree for Large I/O

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Solution Overview

Problem

In large-scale distributed storage systems, existing caching mechanisms face performance overhead due to unnecessary cache operations for large sequential I/O operations, which result in latency and increased memory usage, especially in multi-core environments where lock contention and hash table lookups are prevalent.

Innovation Solution

A cache bypass mechanism utilizing a binary tree structure is implemented to redirect large I/O operations directly to a slower storage tier, bypassing the cache by associating window identifiers with binary trees and using a caching bitmap to minimize latency and memory footprint, thereby avoiding cache overhead and lock contention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If caching mechanisms are used for all I/O operations, then data access speed is improved for small random I/O, but latency increases and memory usage increases for large sequential I/O

Engineering Contradiction:
Improvedata access speedVSAvoidlatency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The system changes the parameter of I/O operation size to determine caching behavior. By comparing the size of each I/O operation against a threshold, the system dynamically adjusts whether to apply caching (for small operations) or bypass caching (for large operations), thereby optimizing both speed and latency based on the specific operation characteristics

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention segments I/O operations into two distinct categories: small random I/O operations that benefit from caching, and large sequential I/O operations that should bypass the cache. This segmentation allows the system to apply different handling strategies to different types of operations, improving overall system performance by avoiding unnecessary cache operations for large I/O

Inventive Principle:
Principle #1Segmentation

2Speed

If caching mechanisms are used for all I/O operations, then data access speed is improved for small random I/O, but memory usage increases

Engineering Contradiction:
Improvedata access speedVSAvoidmemory usage
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The system uses the I/O operation size as a decision parameter to control memory allocation for caching. By changing the parameter threshold for cache eligibility, the system optimizes memory usage by only allocating cache resources to small random I/O operations that actually benefit from caching, while large sequential I/O operations bypass the cache and consume minimal additional memory

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention segments memory usage into cached data for small I/O operations and direct storage paths for large I/O operations. This segmentation prevents unnecessary memory consumption by avoiding cache allocation for large sequential writes, thereby reducing overall memory usage while maintaining fast access speeds for operations that require caching

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If hash table lookups are used for cache management, then cache operations are simplified, but lock contention increases in multi-core environments

Engineering Contradiction:
Improvecache operation simplicityVSAvoidlock contention
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The invention extracts the locking mechanism from the cache management path for large sequential I/O operations. By identifying and removing the unnecessary lock acquisition steps for operations that should bypass the cache, the system eliminates lock contention in multi-core environments while maintaining simplified cache operations for small I/O that do require locking

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system changes the operational parameter based on I/O size: for small I/O operations, it uses hash table lookups with locking to ensure cache consistency, while for large sequential I/O operations, it bypasses the locked cache management path entirely. This parameter-based approach reduces lock contention by avoiding unnecessary lock acquisitions for large I/O while preserving the simplicity of hash table-based cache management for operations that need it

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9779026B2Cache bypass utilizing a binary tree
Publication Date: 2017.10.03 SEAGATE TECH LLC
  • US9779026B2 patent drawing
  • US9779026B2 patent drawing
  • US9779026B2 patent drawing

AI summary

A storage command is received at a block level interface from a file system. The storage command is associated with a window of a virtual drive. One of a plurality of binary trees is selected based on the window being associated with the storage command, each of the binary trees being associated with a plurality of windows. If a data storage size of the storage command exceeds a threshold, a window identifier of the window is added to the selected binary tree to indicate the command will bypass a cache and send data of the storage command directly to main data storage.