Cache Cleaning Circuitry for DDR Memory Page Conflict Reduction
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Solution Overview
Problem
In multiprocessor systems with shared memory, writing data to memory in a time-interleaved fashion leads to non-optimal performance due to frequent page openings and closures in dual data rate (DDR) memory, resulting in delays and decreased system performance.
Innovation Solution
Implementing cache cleaning circuitry that tracks memory accesses to identify when a threshold of dirty cache lines corresponding to the same memory region is reached, allowing for simultaneous cleaning of these lines, thereby reducing the need for continuous page closures and openings, and improving system performance by minimizing delays during the cleaning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is written to memory in a time-interleaved fashion across different pages, then memory bandwidth utilization is improved, but the number of page-opens and page-closes increases, causing performance degradation
Solution Approach 1:
The system performs preliminary tracking of dirty cache lines and their corresponding memory pages before actual write-back operations. By maintaining a data structure that records which pages have dirty cache lines, the system can proactively group write-back operations by page rather than reacting to individual cache line updates, thereby reducing the frequency of page-opens and page-closes
Solution Approach 2:
Multiple individual cache line write-back operations that would normally be performed separately and time-interleaved are merged into batched operations grouped by memory page. This consolidation allows the system to perform fewer page transitions while still updating all modified cache lines, directly reducing the overhead of page-opens and page-closes
2Reliability
If cache lines are cleaned individually in a time-interleaved manner, then cache coherence is maintained, but the number of row conflicts in DDR memory increases, causing delays
Solution Approach 1:
The system preliminarily tracks which cache lines are dirty and group them by their corresponding memory pages before initiating clean operations. This pre-grouping allows the system to perform multiple cache line cleanings within a single row activation window in DDR memory, reducing row conflicts and cleaning delays while maintaining cache coherence
Solution Approach 2:
Multiple individual cache line cleaning operations are merged into batched operations that can be performed within a single memory row activation. By consolidating these operations, the system reduces the number of row conflicts that would otherwise occur with time-interleaved individual cleanings, thereby reducing cleaning delays
Data Source
AI summary
A state indicator associated with a cache line is stored, wherein the cache line is one of a plurality of cache lines each associated with a corresponding unique section of a region of system memory. The state indicator comprises a dirty indication indicating that the cache line is a candidate for writing data stored in the cache line to the associated section of the region of system memory. The state indicator is one of a plurality of state indicators each associated with a corresponding cache line. For the region of system memory, a number of the plurality of state indicators that comprises the dirty indication is determined, and if a threshold is exceeded, data stored in a selected cache line is written to the associated section of the region of system memory, and a clean indication is stored in the state indicator corresponding to the cache line.