Cache Coalescing for Memory Burst Length Utilization
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Solution Overview
Problem
In cache systems, when the native burst length of cache lines is less than that of the memory, it leads to sub-optimal memory access due to inefficient eviction and cleaning operations, resulting in underutilization of memory resources.
Innovation Solution
A method and system where a cache associated with a central processing unit identifies a complementary cache line during eviction, transmitting a single memory instruction to write data from both cache lines to memory, thereby coalescing data to match the memory's native burst length and invalidating only the necessary data in the first cache line, ensuring efficient memory access without affecting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the cache line length is kept shorter than memory burst length for flexibility, then cache management becomes easier, but memory access efficiency deteriorates due to underutilization of memory bandwidth
Solution Approach 1:
The patent merges data from multiple cache lines (first cache line with data to be evicted and second cache line with complimentary data) into a single memory write operation. This combining approach allows the cache to utilize the full memory burst length capability, transforming multiple small writes into one optimized write operation that fully utilizes memory bandwidth.
Solution Approach 2:
The patent segments the memory write operation into two distinct phases: (1) identifying and selecting which cache lines to combine, and (2) executing the combined write operation. This segmentation allows the system to maintain flexible cache line management while achieving optimized memory access through selective combination of data segments.
2Reliability
If separate write operations are used for each cache line eviction, then data integrity is maintained, but memory resource utilization deteriorates due to multiple small transactions
Solution Approach 1:
The patent combines multiple cache line evictions into a single memory write transaction by coalescing data from the first cache line (to be evicted) and the second cache line (complimentary data). This merging maintains data integrity through controlled selection of which lines to combine while significantly improving memory resource utilization by reducing the number of separate transactions.
3Ease of operation
If cache line eviction is performed without coalescing, then operation simplicity is maintained, but memory bandwidth utilization deteriorates due to sub-optimal burst length usage
Solution Approach 1:
The patent performs preliminary action by pre-identifying complimentary cache lines before executing the eviction operation. The cache controller selects which cache lines to combine in advance, preparing the data coalescing operation beforehand. This preliminary identification maintains operational simplicity while enabling optimized memory bandwidth utilization during the actual write operation.
Data Source
AI summary
Embodiments provide a method comprising receiving, at a cache associated with a central processing unit that is disposed on an integrated circuit, a request to perform a cache operation on the cache; in response to receiving and processing the request, determining that first data cached in a first cache line of the cache is to be written to a memory that is coupled to the integrated circuit; identifying a second cache line in the cache, the second cache line being complimentary to the first cache line; transmitting a single memory instruction from the cache to the memory to write to the memory (i) the first data from the first cache line and (ii) second data from the second cache line; and invalidating the first data in the first cache line, without invalidating the second data in the second cache line.