Address Translation Cache Coalescing via Relaxed Attribute Matching
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Solution Overview
Problem
Existing address translation caches face inefficiencies due to limited opportunities for coalescing entries, as the requirements for coalescing are often not met, leading to suboptimal use of circuit resources.
Innovation Solution
An apparatus and method that perform a page table walk to determine if page alignment and attribute match criteria are met, allowing for the generation of coalesced address translation data from adjacent descriptors, even when some attributes differ, thereby increasing the capacity and performance of the address translation cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If existing coalescing requirements are enforced, then address translation cache resources are conserved, but the opportunities to create coalesced entries are limited
Solution Approach 1:
The patent changes the parameters used for coalescing by allowing descriptors with different attribute values to be coalesced into a single entry. Instead of requiring exact attribute matches, the system uses relaxed matching criteria that still ensures correct address translation functionality while enabling more coalescing opportunities.
Solution Approach 2:
The patent creates a more universal coalescing mechanism that can handle a broader range of descriptor variations. By allowing different attribute values in coalesced entries, the system achieves multi-functionality where a single cache entry can represent multiple descriptors with varying attributes, increasing the utility of limited cache resources.
2Quantity of substance
If multiple descriptors are coalesced into a single entry, then address translation cache capacity is increased, but the requirements for coalescing become more restrictive
Solution Approach 1:
The patent modifies the coalescing parameters to be less restrictive, allowing descriptors that previously would not have met the strict matching criteria to be coalesced. This increases the effective cache capacity by enabling more entries to be consolidated while maintaining translation correctness through the updated matching logic.
Solution Approach 2:
The patent segments the attribute matching process into essential and non-essential components. By identifying which attributes must match for correct translation and which can vary, the system enables coalescing of descriptors that would otherwise be excluded, thereby increasing effective cache capacity without sacrificing translation accuracy.
3Reliability
If strict attribute matching is required for coalescing, then translation accuracy is maintained, but cache utilization efficiency decreases
Solution Approach 1:
The patent changes the attribute matching parameters from strict equality to a more flexible matching scheme. This allows descriptors with certain attribute variations to be coalesced while still maintaining translation accuracy by ensuring that the essential translation-critical attributes remain consistent across coalesced descriptors.
Solution Approach 2:
The patent applies different matching strictness to different attributes. Critical attributes that affect translation accuracy maintain strict matching requirements, while non-critical attributes allow for variation. This local differentiation in quality control enables higher cache utilization without compromising translation reliability.
Data Source
AI summary
An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria. Each descriptor comprises physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allows the plurality of descriptors to have different values for a first subset of attributes when determining that the attribute match criteria is met. When the predetermined criteria are met, coalesced address translation data is generated from the plurality of descriptors and that coalesced address translation data is then stored in the selected entry. Otherwise, if the predetermined criteria is not met, address translation data is merely generated from the descriptor identified using the virtual address, and that address translation data is then stored in the selected entry. Such an approach significantly increases the effective capacity and performance of the address translation cache.