Cache Coherence Address Affinization Reduces Die Crossings
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Solution Overview
Problem
In multicore processor systems, the delay in receiving responses to cache coherence queries due to remote device access introduces latency, impacting system performance, particularly due to the need for multiple die-to-die connection crossings and complex address range checks.
Innovation Solution
Implementing a cache coherence solution that optimizes address map organization to minimize die-to-die connection crossings by using address affinization, which allows for direct connections between clusters and reduces the number of range checks, thereby selecting the closest caching agent to the target home agent for cache coherence operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache coherence queries are sent to remote devices to check access or use of cached content, then cache coherence can be maintained across multiple processors, but response time increases due to remote device access latency
Solution Approach 1:
The system segments the address space into local and remote ranges, allowing the coherence controller to quickly determine whether a coherence query should be sent locally or remotely based on the address range, thereby reducing unnecessary remote queries and associated latency
Solution Approach 2:
The system performs preliminary actions by pre-establishing address range mappings and cache coherence states before actual coherence queries are needed, enabling faster decision-making about which caches need to be queried and reducing response time
2Reliability
If multiple die-to-die connection crossings are used to access remote caches, then cache coherence can be maintained across distributed processors, but transfer latency increases due to multiple connection crossings
Solution Approach 1:
The system creates local quality by organizing caches and address spaces so that frequently accessed data and coherence queries can be resolved locally without requiring remote die-to-die connections, thereby maintaining cache coherence while minimizing transfer latency for common operations
3Measurement precision
If complex address range checks are performed to determine cache coherence status, then accurate coherence information can be obtained, but processing time increases due to multiple range check operations
Solution Approach 1:
The address space is segmented into predefined ranges associated with different caches, allowing the coherence controller to quickly determine coherence status by checking which range a given address falls into, rather than performing complex comprehensive range checks, thereby maintaining accuracy while reducing processing time
Data Source
AI summary
Examples described herein relate to processor circuitry to issue a cache coherence message to a central processing unit (CPU) cluster by selection of a target cluster and issuance of the request to the target cluster, wherein the target cluster comprises the cluster or the target cluster is directly connected to the cluster. In some examples, the selected target cluster is associated with a minimum number of die boundary traversals. In some examples, the processor circuitry is to read an address range for the cluster to identify the target cluster using a single range check over memory regions including local and remote clusters. In some examples, issuance of the cache coherence message to a cluster is to cause the cache coherence message to traverse one or more die interconnections to reach the target cluster.