Cache Memory Coherence Controller Dynamic Allocation
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Solution Overview
Problem
In multi-processor systems, maintaining data coherence between level-1 caches and a shared level-2 cache is challenging, leading to issues with normal operation due to outdated data access.
Innovation Solution
A cache memory system with first to Nth level-1 caches, a shared level-2 cache, and a coherence controller that dynamically allocates areas of the level-2 cache based on address reception order and access frequency, using map controllers to manage data allocation and ensure data coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a shared level-2 cache is used by multiple level-1 caches in a multi-processor system, then cache memory capacity is improved, but data coherence is deteriorated due to outdated data access
Solution Approach 1:
The level-2 cache is segmented into multiple regions, with each region allocated to a specific level-1 cache. This segmentation allows each level-1 cache to have dedicated access to its allocated region while sharing the overall level-2 cache structure, thereby maintaining data coherence within allocated regions while providing extended cache capacity
Solution Approach 2:
The cache allocation is made dynamic through the coherence controller, which can allocate and deallocate level-2 cache regions to different level-1 caches based on real-time access patterns and coherence requirements. This dynamic allocation ensures that data coherence is maintained while optimizing cache utilization
2Quantity of substance
If a shared level-2 cache is used by multiple level-1 caches, then cache memory capacity is improved, but access performance is deteriorated due to cache conflicts
Solution Approach 1:
By segmenting the level-2 cache into dedicated regions for each level-1 cache, the patent reduces cache conflicts and contention. Each level-1 cache can access its allocated region without interfering with other level-1 caches, thereby maintaining high access performance while providing extended cache capacity
Solution Approach 2:
The coherence controller acts as an intermediary that manages access to the level-2 cache regions. It receives addresses from level-1 caches, determines the appropriate allocated region, and directs access accordingly, thereby eliminating direct conflicts between multiple level-1 caches while maintaining efficient access performance
Data Source
AI summary
Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.