Multi-Level Cache Coherence via External Essence State Tracking

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Solution Overview

Problem

Traditional cache coherence protocols, such as MESI and MOESI, have limitations in efficiency due to their complexity and bandwidth usage, particularly in managing cache line states and write-back operations across different memory levels.

Innovation Solution

Implementing multiple information state tracking approaches or protocols at different memory levels, where local state indications are used for simpler implementations like MESI and essence state indications are tracked externally to enable more efficient protocols like MOESI, allowing for refined state management and reduced DRAM bandwidth consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If MESI protocol is used for cache coherence management, then implementation complexity is reduced, but DRAM bandwidth consumption increases due to unnecessary write-backs

Engineering Contradiction:
Improvecache coherence protocol implementation complexityVSAvoidDRAM bandwidth consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The patent segments the coherence protocol into two distinct parts: local MESI state tracking at the cache level and external essence state tracking at the directory level. This segmentation allows each component to operate with its own simplified state machine while the combined system achieves MOESI-level efficiency. The local cache only needs to track MESI states, keeping implementation simple, while the external directory tracks essence states to prevent unnecessary write-backs, thereby reducing DRAM bandwidth consumption.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If MOESI protocol is used for cache coherence management, then DRAM bandwidth efficiency is improved, but implementation complexity increases due to additional state tracking requirements

Engineering Contradiction:
ImproveDRAM bandwidth consumptionVSAvoidcache coherence protocol implementation complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent introduces an external directory as an intermediary between the local cache and the DRAM. This directory tracks the essence state of cache lines independently from the local cache state. When a cache line needs to be evicted, the system queries the external directory to determine if a write-back is actually necessary, rather than blindly writing back based solely on local state. This intermediary approach achieves MOESI-level bandwidth efficiency while keeping the local cache implementation relatively simple.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If traditional single-level coherence protocols are used, then protocol implementation is simpler, but overall system performance is limited due to bandwidth inefficiency

Engineering Contradiction:
Improvecoherence protocol structureVSAvoidsystem performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent adds a new dimension to traditional coherence protocols by introducing an external state tracking layer that operates parallel to the local cache state tracking. Instead of merely extending the state machine within the cache (as in MOESI), the invention creates a two-dimensional state tracking system: local MESI states for fast decision-making and external essence states for bandwidth optimization. This dimensional addition enables the system to achieve higher performance without proportionally increasing local cache complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9824009B2Information coherency maintenance systems and methods
Publication Date: 2017.11.21 NVIDIA CORP
  • US9824009B2 patent drawing
  • US9824009B2 patent drawing
  • US9824009B2 patent drawing

AI summary

Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or storage levels. In one embodiment, a first coherency maintenance approach (e.g., similar to a MESI protocol, etc.) can be implemented at one storage level while a second coherency maintenance approach (e.g., similar to a MOESI protocol, etc.) can be implemented at another storage level. Information at a particular storage level or tier can be tracked by a set of local state indications and a set of essence state indications. The essence state indication can be tracked “externally” from a storage layer or tier directory (e.g., in a directory of another cache level, in a hub between cache levels, etc.). One storage level can control operations based upon the local state indications and another storage level can control operations based in least in part upon an essence state indication.