Cache Coherence Protocol Explicit Control States
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Solution Overview
Problem
In multi-processor environments, cache coherence protocols lead to significant messaging overhead and performance degradation due to the need for frequent invalidate and acknowledge messages to maintain coherency across shared cache lines.
Innovation Solution
Implementing a method that allows cache lines to be set to an explicit control state, either private or read-only, where only predetermined memory access operations are permitted, and these operations are not tracked by a global directory, reducing the need for invalidate and acknowledge messages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cache coherence protocol is implemented to maintain coherent shared memory across multiple processors, then cache corruption is avoided, but messaging overhead increases and system performance degrades
Solution Approach 1:
The patent segments the cache coherency management by dividing cache lines into two categories: those tracked by the global directory and those in explicit control states. This segmentation allows the system to apply full coherence protocols only where necessary while eliminating overhead for lines in explicit control states, thereby reducing overall messaging complexity while maintaining reliability.
Solution Approach 2:
The patent introduces explicit control states (read-only and private) as new parameter values for cache lines. When a cache line is in one of these states, the global directory stops tracking it, fundamentally changing the coherency management parameters from active tracking to passive enforcement, which reduces messaging overhead while preserving coherency where needed.
2Reliability
If the global directory tracks all memory access operations to maintain coherency, then cache corruption is prevented, but system performance decreases due to frequent messaging
Solution Approach 1:
The patent extracts cache lines from the global directory tracking system by placing them in explicit control states. Once extracted, these lines no longer generate invalidate and acknowledge messages, directly improving system performance while coherency is maintained through the explicit state constraints that prevent corruption without requiring directory intervention.
Solution Approach 2:
The patent applies preliminary action by setting cache lines to explicit control states (read-only or private) before they would otherwise require tracking. This preliminary classification allows the system to preemptively eliminate messaging overhead for certain cache lines while maintaining coherency through the state-based access control, thereby improving performance without sacrificing reliability.
3Device complexity
If cache lines are allowed in explicit control states with restricted memory operations, then messaging overhead is reduced, but flexibility in memory access operations decreases
Solution Approach 1:
The patent introduces dynamics by allowing cache lines to transition between different states (tracked and explicit control states) based on access patterns and requirements. This dynamic state management enables the system to adaptively reduce protocol complexity for appropriate cache lines while maintaining flexibility for those that require full tracking, effectively balancing complexity reduction with access flexibility.
Data Source
AI summary
One embodiment of the present invention sets forth am extension to a cache coherence protocol with two explicit control states, P (private), and R (read-only), that provide explicit program control of cache lines for which the program logic can guarantee correct behavior. In the private state, only the owner of a cache line can access the cache line for read or write operations. In the read-only state, only read operations can be performed on the cache line, thereby disallowing write operations to be performed.