Duplicated Cache Coherence Interconnects for Fault Detection
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Solution Overview
Problem
Cache coherence systems in system-on-chip designs face significant wire routing congestion due to the centralized nature of cache coherence, which can lead to errors in extreme environments where reliability is critical, such as automotive or aviation applications.
Innovation Solution
The separation of cache coherence functions into distinct units, including Agent Interface Units, Coherence Controller Units, and Memory Interface Units, coupled through a transport network, allows for logical and physical separation, reducing congestion and enabling error detection and correction by duplicating coherent interconnect units and using a comparator for fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized monolithic cache coherent system IP is used, then the system structure is simple, but wire routing congestion increases significantly
Solution Approach 1:
The patent divides the centralized monolithic cache coherent system into multiple separate coherent interconnect units, each handling specific coherence operations. This segmentation distributes the wire routing load across multiple smaller units rather than requiring a single large centralized hub, thereby reducing wire routing congestion while maintaining system functionality.
2Reliability
If duplicate coherent interconnect units are added for error checking, then error detection capability improves, but device complexity increases
Solution Approach 1:
The patent implements duplicate coherent interconnect units where one unit performs the normal coherence operation while the other unit performs the same operation for error detection and correction purposes. This copying approach enables error detection capability by comparing outputs from both units, and the patent optimizes this duplication to minimize the increase in device complexity.
3Adaptability or versatility
If more agents and memory interfaces are integrated, then system functionality improves, but wire routing congestion worsens
Solution Approach 1:
The patent segments the coherence system into multiple independent coherent interconnect units that can be distributed across the chip. This allows more agents and memory interfaces to be integrated without concentrating all connectivity requirements at a single centralized point, thereby reducing wire routing congestion while supporting increased system functionality.
Data Source
AI summary
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.