Cache Coherence Manager for Heterogeneous Processor Systems

The patent introduces a cache coherence manager as an intermediary component that mediates data movement between CPU cache and GPU cache. This manager tracks data locations, manages coherence protocols, and coordinates transfers, thereby improving data availability while containing the complexity of coherence maintenance within a dedicated management layer rather than distributed across all processors.

The system performs preliminary actions by pre-copying data from CPU cache to GPU cache before the GPU actually needs it for processing. The coherence manager monitors data access patterns and initiates data transfers in advance, ensuring data is available when needed while reducing the urgency and complexity of real-time coherence management.

The cache coherence manager implements feedback mechanisms by monitoring data access patterns, tracking which data resides in which caches, and receiving notifications when processors access or modify data. This feedback enables the system to maintain consistency by responding to actual data usage events, ensuring that copies in CPU cache and GPU cache remain synchronized with main memory without continuously checking all data.

The coherence manager acts as an intermediary between the caches and main memory, intercepting and coordinating data access operations. It manages the complexity of maintaining consistency across multiple caches by centralizing coherence control, thereby enabling fast cache access while preserving data reliability through coordinated updates.

The system performs data movement in advance by monitoring when data is loaded into CPU cache and proactively copying it to GPU cache before the GPU needs it. This preliminary action eliminates or reduces the actual data movement time when the GPU starts processing, as the data is already in place. The coherence manager tracks data lifecycles and initiates transfers during idle periods or before scheduled GPU operations.

The data movement system is made dynamic by adapting transfer timing and triggers based on actual processor behavior and data access patterns. Rather than using fixed scheduling, the coherence manager responds to dynamic events such as data insertion into CPU cache, processor idle states, and predicted GPU needs, optimizing data movement timing to minimize overhead while maintaining processor flexibility.