Directory-Based Cache Coherence for Ordered Parallel Writes
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Solution Overview
Problem
In multi-core electronic systems, ordered writes to different targets can be completed out of order, and existing directory-based protocols ensure order only within their own slice of memory, necessitating serial completion of writes before proceeding, which is inefficient.
Innovation Solution
A directory-based method that involves acquiring early ownership of cache lines for writes in a multi-core electronic system, allowing parallel streaming of writes to multiple targets while maintaining ordered write observation, with a network-on-chip (NoC) facilitating this through initiator and target network interface units (NIUs) to manage cache coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If writes are serialized through a single directory to ensure order, then cache coherence is maintained, but write throughput decreases due to serial processing
Solution Approach 1:
The system segments the directory functionality by distributing directories across multiple cores, with each directory managing a specific slice of memory addresses. This allows parallel write operations to different memory slices to proceed simultaneously without serializing through a single directory, thereby improving write throughput while maintaining cache coherence within each slice.
Solution Approach 2:
The patent introduces an initiator interface unit as an intermediary between the core and directories. This unit acquires ownership of cache lines on behalf of the core and manages the serialization of writes to multiple targets, allowing the core to issue writes in parallel while the intermediary ensures proper ordering and coherence through targeted directory communications.
2Reliability
If waits for writes to one target to finish before sending writes to next target, then write order is guaranteed, but latency increases
Solution Approach 1:
The initiator interface unit performs preliminary actions by acquiring ownership of cache lines for multiple targets in advance, before the actual write operations complete. This allows subsequent writes to be issued in parallel to multiple targets without waiting for previous writes to finish, reducing latency while maintaining order through the ownership mechanism.
Solution Approach 2:
The system changes the dimension of ordering from sequential target-by-target processing to parallel processing across multiple targets with ownership-based serialization. Writes can be issued to multiple targets simultaneously in different dimensions of the memory space, with the initiator interface unit managing the ordering relationship across these parallel operations.
3Productivity
If each directory ensures order only within its own slice, then scalability improves, but global write order across different slices is lost
Solution Approach 1:
The initiator interface unit serves multiple functions: it manages cache line ownership, serializes writes to multiple targets, and ensures global write order across different directory slices. This universal intermediary component coordinates across the distributed directory structure, maintaining both the scalability of individual directories and the global ordering requirement.
4Reliability
If a single directory is used for all memory addresses, then write ordering is maintained, but device complexity and bottleneck increase
Solution Approach 1:
The directory structure is segmented into multiple distributed directories, each managing a specific slice of memory addresses. This segmentation reduces the complexity and memory requirements of each individual directory while maintaining write ordering through the initiator interface unit that coordinates across slices and manages cache line ownership.
Data Source
AI summary
In a multi-core electronic system, a directory-based method of processing a request transaction includes, upon receipt of the request transaction, communicating with a plurality of directories to acquire ownership of cache lines to establish a single point of serialization. Write data is thereafter streamed to owned cache lines in at least two targets in parallel while keeping ordered write observation. The writes to the at least two targets are processed out of order but observed in order.