Cache Coherence Interconnect Redundancy for Wire Congestion Relief
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Solution Overview
Problem
Cache coherence systems in system-on-chip designs face significant wire routing congestion due to centralized monolithic cache coherence units, which can lead to errors in extreme environments where reliability is critical, such as automotive or aviation applications.
Innovation Solution
The separation of cache coherence functions into distinct units, including Agent Interface Units, Coherence Controller Units, and Memory Interface Units, coupled through a transport network, allowing for independent scaling and error detection/correction by duplicating coherent interconnect units and using a comparator for fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a centralized monolithic cache coherent system IP is used, then system simplicity is maintained, but wire routing congestion increases significantly
Solution Approach 1:
The patent divides the centralized monolithic cache coherent system IP into multiple separate coherent interconnect units, each handling specific coherence operations. This segmentation reduces the wiring burden on any single route by distributing coherence traffic across multiple independent units, thereby resolving the wire routing congestion issue while maintaining manageable system complexity through modular architecture
2Reliability
If duplicate coherent interconnect units are added for error checking, then reliability improves, but device complexity increases
Solution Approach 1:
The patent implements error detection by creating duplicate copies of coherent interconnect units that mirror the functional units. These checker units receive the same inputs and produce outputs that are compared with the functional units' outputs. The copying approach provides robust error detection capability while the modular nature of the units keeps the complexity increase manageable through standardized replication
Data Source
AI summary
A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.