Instruction and Data Cache Coherence for Self-Modifying Code
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Solution Overview
Problem
Emulating a microprocessor with an internal memory too small to hold 2 MB of main memory requires an efficient caching strategy to reduce external memory accesses, but this hinders the emulation of self-modifying code due to the need to cache data writes, which are not typically handled in cache-based systems.
Innovation Solution
Implementing a data processing system with a direct-mapped instruction cache and a fully associative data cache that allows for caching of data writes and reads, where data is stored in the cache until the page is written back to main memory, and using DMA for external memory access, ensuring cache coherence without direct write-back to main memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a caching strategy is implemented to reduce external memory accesses, then access speed is improved, but the ability to handle self-modifying code deteriorates
Solution Approach 1:
The patent divides the caching system into two separate caches: an instruction cache for storing instructions and a data cache for storing data. This segmentation allows each cache to be optimized for its specific purpose, with the data cache able to handle writes while the instruction cache maintains coherence for self-modifying code scenarios.
Solution Approach 2:
The patent introduces a memory management unit (MMU) as an intermediary between the caches and main memory. The MMU tracks write operations and manages cache coherence, acting as a mediator that enables self-modifying code to work correctly while still benefiting from caching performance improvements.
2Productivity
If data writes are cached to reduce external memory accesses, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent separates the caching functionality into distinct instruction and data caches, allowing simpler individual cache designs while achieving overall system efficiency. The data cache handles writes with the understanding that coherence will be managed separately by the MMU.
Solution Approach 2:
The data cache operates autonomously to handle data writes without requiring complex coherence protocols within the cache itself. The cache simply stores writes locally, and the MMU handles the coordination with main memory, allowing the cache to serve itself while maintaining system-wide consistency.
3Loss of substance
If local memory is kept small to reduce cost, then loss of substance is reduced, but loss of time increases due to more external accesses
Solution Approach 1:
The patent implements caching that stores copies of data and instructions in local memory before they are needed from main memory. This preliminary action of pre-loading data into caches reduces the frequency of slow external memory accesses, trading a small amount of local memory for significant time savings.
Solution Approach 2:
The patent optimizes local memory usage by creating specialized caches with specific characteristics optimized for their purposes. The instruction cache is optimized for instruction fetch patterns while the data cache handles data access patterns, making efficient use of limited local memory resources.
Data Source
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AI summary
A data processor comprises a main memory; an instruction cache and a data cache; instruction fetch logic operable to search the instruction cache for a required instruction; and if the required instruction is not present in the instruction cache, to search the data cache; and if the required instruction is not present in the data cache, to fetch the required instruction from the main memory to the instruction cache; data write logic operable to write a data value into the data cache at a data address and, if that address is also represented in the instruction cache, to write that data value into the instruction cache; and cache control logic operable to transfer data from the data cache to the main memory.