L2 Cache Coherence State Remapping During L1 Cache Resizing

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Solution Overview

Problem

Existing multi-level cache systems face inefficiencies in managing cache coherence and size changes, leading to performance bottlenecks and increased latency in data access.

Innovation Solution

Implementing a method and apparatus that involve a L1 controller managing cache size changes and stalling requests, while a L2 controller flushes pipelines and reinitializes shadow caches, along with updating coherence states in response to cache line relocations and requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the L1 cache size is changed dynamically, then cache management flexibility is improved, but cache coherence complexity increases

Engineering Contradiction:
Improvecache management flexibilityVSAvoidcache coherence complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The L2 controller performs preliminary actions by flushing its pipeline and reinitializing the shadow L1 cache before the actual L1 cache size change occurs. This preparation ensures that the L2 cache is in a consistent state and ready to handle coherence operations after the L1 cache configuration changes, thereby managing the coherence complexity that arises from dynamic size changes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The shadow L1 cache in the L2 controller acts as an intermediary structure that mirrors the L1 main cache state. When the L1 cache size changes, the shadow cache is reinitialized to reflect the new configuration, providing a bridge that maintains coherence information without requiring immediate changes to all active cache operations, thus managing coherence complexity while enabling flexible size changes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If cache size changes are performed, then cache adaptability is improved, but request handling time increases

Engineering Contradiction:
Improvecache adaptabilityVSAvoidrequest handling time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The L2 controller performs preliminary pipeline flushing and shadow cache reinitialization before the L1 cache size change takes effect. This preliminary action ensures that pending requests are cleared and the coherence state is prepared in advance, minimizing the impact on active request handling during the cache size transition and reducing overall request handling time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The L1 controller stalls new requests during the cache size change operation and services only pending requests before the change. This approach skips or bypasses the complexity of handling new coherence operations during the transition, focusing resources on completing existing operations quickly and minimizing the time new requests wait during the reconfiguration.

Inventive Principle:
Principle #21Skipping (Rushing through)

3Reliability

If shadow cache reinitialization is performed, then cache coherence is improved, but processing steps increase

Engineering Contradiction:
Improvecache coherenceVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The L2 controller maintains a shadow copy of the L1 main cache state in its shadow L1 cache. When the L1 cache size changes, instead of tracking every individual change across the system, the shadow cache is simply reinitialized to match the new configuration. This copying approach simplifies coherence management by providing a centralized reference that automatically reflects the current state, reducing the complexity of tracking coherence across dynamic changes.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The shadow L1 cache serves multiple functions: it mirrors the L1 main cache state for coherence tracking, provides a reference for the L2 controller during size changes, and enables consistent coherence operations across different cache configurations. This multi-functionality consolidates several coherence management tasks into a single structure, reducing the overall processing steps needed to maintain coherence during dynamic size changes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12625809B2Cache coherence shared state suppression
Publication Date: 2026.05.12 TEXAS INSTRUMENTS INC
  • US12625809B2 patent drawing
  • US12625809B2 patent drawing
  • US12625809B2 patent drawing

AI summary

A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.