Physical Address Proxy for Virtually Indexed Cache Coherency
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Solution Overview
Problem
Cache memories in microprocessors impact performance due to access time and cache coherency issues, particularly in multi-processor systems, where ensuring consistent data across shared caches is challenging, and reducing cache memory size and processing overhead can improve processor efficiency.
Innovation Solution
Implementing a cache memory subsystem with first-level and second-level set-associative caches using an inclusive allocation policy, where a physical address proxy (PAP) is used to manage cache coherency, allowing efficient allocation and eviction of cache lines across levels, and virtually-indexed first-level caches with physically-indexed second-level caches to optimize cache performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache memory size is increased to improve hit rates, then processor performance is improved, but physical size and cost increase
Solution Approach 1:
The patent implements a nested cache hierarchy where L1 caches are embedded within L2 caches. Each L1 cache is a subset of the L2 cache, allowing the system to achieve the performance benefits of multiple cache levels while using less total physical memory capacity. The L1 cache lines are allocated from the L2 cache space, creating a nested structure that reduces overall cache footprint while maintaining hit rates.
Solution Approach 2:
The patent creates copies of cache lines across multiple cache levels. When data is accessed, it is copied into both L1 and L2 caches, allowing either level to service the request. This copying mechanism enables the system to achieve high hit rates with smaller individual cache sizes, as the same data can be served from either L1 or L2.
2Reliability
If cache coherency protocols are implemented in multi-processor systems, then data consistency is improved, but processing overhead and complexity increase
Solution Approach 1:
The patent introduces a coherency manager as an intermediary component that handles cache coherency operations. The coherency manager receives coherency requests from multiple processors, manages the state of cache lines across L1 and L2 caches, and coordinates invalidation or update operations. This intermediary approach simplifies the complexity by centralizing coherency management rather than implementing distributed coherency protocols across all processors.
Solution Approach 2:
The patent implements feedback mechanisms where the coherency manager monitors cache line states and processor requests, then responds with appropriate coherency actions. The system tracks the state of each cache line (valid, invalid, dirty, shared) and uses this feedback information to determine whether to invalidate, update, or maintain cache lines, thereby maintaining data consistency with controlled complexity.
3Speed
If cache access time is reduced to improve instruction execution rate, then processor performance is improved, but cache size may be reduced
Solution Approach 1:
The patent segments the cache system into multiple levels with different access characteristics. L1 caches provide fast access for frequently used data, while L2 caches provide larger capacity for less frequently accessed data. The segmentation allows the system to optimize for speed at the L1 level while using L2 to compensate for reduced L1 capacity, thereby reducing overall access time without sacrificing total cache capacity.
Solution Approach 2:
The patent adds a temporal dimension to cache management by implementing an inclusive allocation policy where L1 cache lines are allocated from L2 cache space. This creates a time-based hierarchy where recently accessed data resides in L1 for fast access, while the L2 cache maintains a superset of data for slightly slower but still fast access. This dimensional approach allows reduced L1 size without proportionally increasing access time.
Data Source
AI summary
A cache memory subsystem includes virtually-indexed L1 and PIPT L2 set-associative caches having an inclusive allocation policy such that: when a first copy of a memory line specified by a physical memory line address (PMLA) is allocated into an L1 entry, a second copy of the line is also allocated into an L2 entry; when the second copy is evicted, the first copy is also evicted. For each value of the PMLA, the second copy can be allocated into only one L2 set, and an associated physical address proxy (PAP) for the PMLA includes a set index and way number that uniquely identifies the entry. For each value of the PMLA there exist two or more different L1 sets into which the first copy can be allocated, and when the L2 evicts the second copy, the L1 uses the PAP of the PMLA to evict the first copy.