Cache Coherency Controller Back Invalidation Selection
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Solution Overview
Problem
Cache coherency controllers face inefficiencies due to high rates of back invalidations, which reduce cache hits and increase power consumption and memory access times, especially when dealing with cache memories that do not properly notify evictions.
Innovation Solution
A cache coherency controller that selectively targets back invalidations towards cache memories based on their operational performance and likelihood of incorrect eviction notifications, using a directory to track cache usage and adjust the selection of directory entries to be overwritten based on the performance metrics of each cache memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If back invalidation is performed to maintain directory inclusivity, then cache coherency is maintained, but cache hit rate decreases and power consumption increases
Solution Approach 1:
The patent changes the parameter of directory entry selection from uniform/random to selective based on cache behavior metrics. By monitoring which caches properly signal evictions versus those that don't, the system dynamically adjusts which caches receive back invalidations, changing the operational parameters of the coherence protocol to reduce unnecessary invalidations while maintaining coherency.
2Reliability
If back invalidation is performed frequently to maintain directory accuracy, then directory inclusivity is maintained, but memory access time increases
Solution Approach 1:
The system changes the frequency and target selection parameter of back invalidations based on observed cache behavior. Caches that properly signal evictions are targeted less frequently, while caches with poor signaling are targeted more selectively, optimizing the balance between directory accuracy and access time.
3Device complexity
If uniform back invalidation is applied to all caches, then simplicity of implementation is maintained, but efficiency decreases due to unnecessary invalidations
Solution Approach 1:
The patent applies local quality by differentiating the treatment of individual caches based on their specific behavior characteristics. Each cache is evaluated independently on its eviction signaling accuracy, and back invalidations are selectively applied to specific caches rather than uniformly to all, optimizing overall system efficiency.
Solution Approach 2:
The system implements feedback by monitoring whether caches properly signal evictions to the coherence controller. This observed behavior feeds back into the decision-making process for selecting which caches to send back invalidations to, creating a closed-loop system that adapts to actual cache performance.
Data Source
AI summary
A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be overwritten, from the set of directory entries, in dependence upon which of the group of two or more cache memories is indicated by that directory entry, according to a likelihood of selection amongst the two or more cache memories.