Cache Coherency Directory for Multiprocessor Contention
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Solution Overview
Problem
In multiprocessor environments with shared cache lines, existing cache coherency mechanisms face challenges in managing cache line ownership and preventing contention between processors, leading to potential inconsistencies and inefficiencies in cache management.
Innovation Solution
A cache memory coherency system is introduced that utilizes a shared address space across multiple processors, employing a store address list, fetch address list, priority and pipeline module, request tracker module, and read/write address list to manage cache line requests and ensure coherency through status bit tracking and deferred state management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache lines are shared across multiple processors to improve memory utilization, then productivity is improved, but cache coherency and consistency deteriorate due to contention and ownership conflicts
Solution Approach 1:
The patent introduces a coherency directory as an intermediary structure that tracks ownership and validity states of cache lines across multiple processors. This directory acts as a mediator that coordinates access between processors, resolving contention without sacrificing memory utilization. The directory maintains state information (valid, modified, shared) that enables coherent cache management while allowing multiple processors to efficiently access shared memory.
2Reliability
If cache ownership is strictly managed to prevent inconsistencies, then cache coherency is improved, but device complexity increases due to ownership tracking mechanisms
Solution Approach 1:
The patent segments the cache coherency management into distinct functional components: a coherency directory for tracking ownership, validity bits for state monitoring, and snoop logic for inter-processor coordination. This segmentation allows each component to handle specific aspects of coherency management independently, reducing overall system complexity while maintaining reliable cache coherency across multiple processors.
3Productivity
If cache lines are evicted to accommodate new lines, then productivity is improved through better cache utilization, but loss of time occurs due to eviction overhead and potential re-fetching
Solution Approach 1:
The patent implements preliminary actions by pre-tracking cache line ownership and validity states in the coherency directory before eviction is needed. When a cache line needs to be evicted, the system checks the directory to determine if the line is shared or modified, and performs appropriate actions (invalidation, write-back, or simple eviction) in advance. This preliminary tracking eliminates costly runtime checks and reduces eviction overhead, maintaining high cache utilization with minimal time loss.
Data Source
AI summary
A system provides a cache memory coherency mechanism within a multi-processor computing system utilizing a shared memory space across the multiple processors. The system possesses a store address list for storing cache line addresses corresponding to a cache line write request issued by one of the multiple processors, a fetch address list for storing cache line addresses corresponding to a cache line fetch request issued by one of the multiple processors, a priority and pipeline module, a request tracker module and a read/write address list. The store address list and the fetch address list are queues containing result in cache lookup requests being done by the priority and pipeline module; and each entry in the store address list and the fetch address list possess status bits which indicate the state of the request.