Multi-Category Cache Coherency Directory Segmentation
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Solution Overview
Problem
Multiprocessor shared memory systems face inefficiencies in cache coherency management as directory sizes increase with system memory, leading to higher resource consumption and scalability issues, particularly in hardware-managed protocols that require extensive memory access for state and ownership tracking.
Innovation Solution
Implementing a system that categorizes memory blocks into three categories with distinct cache coherency protocols: hardware-managed with a coherency directory cache, hardware-managed with a directory on the node controller, and software-managed, allowing for optimal resource allocation and minimizing resource consumption by leveraging the advantages of each protocol.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware-managed cache coherency protocols are used with increasing system memory, then cache coherency tracking capability is improved, but directory size and memory consumption increase
Solution Approach 1:
The patent segments the cache coherency management into two parts: a compressed directory stored in system memory that tracks all memory blocks, and a directory cache stored in the node controller that holds frequently accessed state and ownership information. This segmentation allows the system to maintain comprehensive tracking capability while reducing the amount of memory needed in the node controller.
Solution Approach 2:
The patent extracts the most frequently accessed directory information (state and ownership of specific memory blocks) from the full directory stored in system memory and places it in a separate directory cache in the node controller. This extraction allows fast access to critical coherency information without requiring the entire directory to reside in the node controller's limited memory.
2Reliability
If directory size increases to track more memory blocks, then cache coherency coverage is improved, but access time and resource consumption increase
Solution Approach 1:
The patent pre-loads state and ownership information for frequently accessed memory blocks into the directory cache before they are needed for coherency operations. By anticipating future access patterns and preparing the directory cache in advance, the system minimizes access time when coherency checks are performed, while still maintaining comprehensive coverage through the full directory in system memory.
3Measurement precision
If extensive memory access is used for state and ownership tracking, then cache coherency accuracy is improved, but system performance deteriorates
Solution Approach 1:
The patent implements local quality by providing different levels of directory information storage based on access frequency and criticality. The system maintains a complete, accurate directory in system memory for all memory blocks, while maintaining a smaller, optimized directory cache in the node controller for fast access to frequently accessed blocks. This local optimization ensures accuracy where needed while improving overall system performance.
Data Source
AI summary
In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.