Cache Coherency Domain Index for Disaggregated Data Centers
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Solution Overview
Problem
Existing cache coherency solutions in multi-CPU systems are inefficient, leading to high cache coherency traffic and resource strandedness, which limits the scalability of applications across multiple CPU sockets and hinders the vision of a 'data center as a single computer' due to broadcast-based protocols that do not scale well with disaggregated data center architectures.
Innovation Solution
A mechanism is introduced in a disaggregated data center architecture that uses a coordinating entity to determine a cache coherency domain index, configuring communicating entities like gateways to direct and filter cache coherency traffic, thereby grouping processor cores into a single cache coherency domain and optimizing messaging, reducing unnecessary communication and resource wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If broadcast-based cache coherency protocols are used in multi-CPU systems, then cache coherency is maintained across all processor cores, but cache coherency traffic increases significantly and does not scale well with disaggregated data center architectures
Solution Approach 1:
The patent segments the cache coherency domain by introducing a domain index that divides processor cores into separate coherency groups. Instead of maintaining coherency across all cores in the system, the segmentation allows each domain to maintain coherency independently, reducing the broadcast traffic scope while preserving reliability within each segmented domain.
2Reliability
If broadcast-based cache coherency protocols are used across multiple CPU sockets, then all processor cores maintain synchronized cache data, but resource strandedness increases and scalability is limited
Solution Approach 1:
The patent applies segmentation by creating multiple cache coherency domains using a domain index, allowing different groups of processor cores to operate independently. This enables the system to scale to more CPU sockets and cores without requiring all cores to participate in every coherency transaction, thus improving productivity and scalability while maintaining data synchronization within each domain.
Solution Approach 2:
The patent implements local quality by allowing different cache coherency behaviors and domains to exist in different parts of the system. Each domain can be optimized for its specific workload and topology, with the domain index enabling local coherency management rather than a uniform global approach, thereby enhancing system scalability and resource utilization.
3Adaptability or versatility
If existing cache coherency solutions are implemented in disaggregated data center architectures, then multi-CPU systems can access memory across sockets, but high cache coherency traffic and resource wastage occur
Solution Approach 1:
The patent segments the disaggregated data center architecture into multiple cache coherency domains using a domain index. This allows memory access across sockets to be maintained while reducing coherency traffic by limiting broadcasts to only those domains that need to participate, rather than forcing all processor cores in the disaggregated system to handle every memory access event.
Solution Approach 2:
The patent introduces the domain index as an intermediary mechanism that mediates between memory access requests and cache coherency broadcasts. The domain index acts as a filter that determines which processor cores should receive coherency notifications, reducing unnecessary traffic in disaggregated architectures while maintaining the ability to access memory across sockets when needed.
Data Source
AI summary
A method performed by a coordinating entity in a disaggregated data center architecture wherein computing resources are separated in discrete resource pools and associated together to represent a functional server. The coordinating entity obtains a setup of processor cores that are coupled logically as the functional server, and determines an index indicating an identity of a cache coherency domain based on the obtained setup of processor cores. The coordinating entity further configures one or more communicating entities associated with the obtained setup of processor cores, to use the determined index when handling updated cache related data.