Cache Coherency Protocol for Domain Shared State

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Solution Overview

Problem

Current hardware configurations face challenges in executing functional-safety critical code alongside non-functional-safety critical code due to resource interference, particularly in shared caches, which can lead to faults in safety-critical domains, necessitating separate resources to ensure Freedom From Interference (FFI).

Innovation Solution

Implementing a cache coherency protocol that allows sharing of cache lines between real-time and non-real-time domains by indicating domain shared states, using mechanisms like page table entries to manage cache coherency and restrict interference to explicitly shared resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If shared cache resources are used between real-time and non-real-time domains, then hardware cost and complexity are reduced, but interference between domains occurs compromising safety-critical operations

Engineering Contradiction:
Improvehardware complexityVSAvoidsafety-critical operation reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The cache system is segmented into real-time cache and non-real-time cache domains, with further segmentation into shared and private cache lines. This allows selective sharing of cache resources while maintaining isolation for safety-critical operations, resolving the contradiction between hardware complexity and reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different cache lines have different sharing attributes (shared vs. private) based on their safety-criticality. Real-time cache lines can be marked as shared or private, allowing local optimization where non-critical data shares cache resources while critical data maintains exclusive access, balancing complexity and reliability.

Inventive Principle:
Principle #3Local quality

2Reliability

If separate cache resources are allocated to ensure Freedom From Interference, then reliability is improved, but hardware cost and complexity increase

Engineering Contradiction:
ImproveFreedom From InterferenceVSAvoidhardware complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cache controller is designed to handle multiple functions: managing both real-time and non-real-time domains, supporting shared and private cache lines, and implementing coherency protocols. This multi-functionality allows a single cache structure to provide both sharing and isolation, improving reliability without proportionally increasing hardware complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The cache sharing attributes are dynamic and can be configured per cache line rather than fixed for entire cache structures. This allows the system to adaptively allocate cache resources, providing isolation only where needed for safety-critical operations while allowing sharing elsewhere, thus improving reliability without unnecessary hardware complexity.

Inventive Principle:
Principle #15Dynamics

3Productivity

If speculation and caching mechanisms are used, then performance is improved, but interference between safety-critical and non-safety critical code occurs

Engineering Contradiction:
Improvehardware performanceVSAvoidsafety-critical code reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The cache is segmented into real-time and non-real-time domains with distinct coherency protocols. Non-real-time speculative operations are isolated from real-time critical operations, allowing performance optimization through speculation while preventing interference with safety-critical code execution.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The cache controller acts as an intermediary that manages coherency between real-time and non-real-time domains. It mediates access to shared cache lines, ensuring that speculative operations in non-real-time domains do not compromise the reliability of real-time operations, thus maintaining both performance and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4254202B1Cache coherency protocol for encoding a cache line with a domain shared state
Publication Date: 2024.04.24 WOVEN BY TOYOTA INC
  • EP4254202B1 patent drawingFigure 1
  • EP4254202B1 patent drawingFigure 2
  • EP4254202B1 patent drawingFigure 3

AI summary

A system, method, and storage medium are provided. The system includes a real-time domain including a real-time cache and a non-real-time domain including a non-real-time cache. The system is configured to implement a cache coherency protocol by indicating that a cache line may be shared between the real-time cache and the non-real-time cache.