Cache Coherency Error Recovery in Shared Memory Systems

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Solution Overview

Problem

Conventional information processing systems with shared memory fail to maintain cache coherency when errors occur, as cached data is not discarded and directory normalization is not performed until the data causing the error is accessed again, leading to incomplete error correction and potential system reboot requirements.

Innovation Solution

An information processing system that detects errors by discarding acquired data in the cache of the CPU and normalizing the directory, ensuring cache coherency by instructing other processing units to discard data and update state management information, thereby preventing cache coherency errors and allowing the system to recover without rebooting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If cached data is not discarded when errors occur, then system operation continues without interruption, but cache coherency is not maintained and errors propagate

Engineering Contradiction:
Improvecache coherencyVSAvoidsystem continuity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by detecting errors through timeout mechanisms before they propagate, and immediately discarding cached data and normalizing directories to prevent coherency errors, thus maintaining reliability while minimizing interruption to system operation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where nodes monitor communication routes and detect errors through timeout conditions, then respond by discarding cached data and updating directory information, creating a closed-loop control that maintains cache coherency while allowing continuous operation

Inventive Principle:
Principle #23Feedback

2Reliability

If directory normalization is not performed until data causing error is accessed again, then system operation is simpler, but error correction is incomplete and system reboot is required

Engineering Contradiction:
Improveerror correction completenessVSAvoiderror handling process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system performs directory normalization and cached data discarding as preliminary actions immediately when errors are detected, rather than waiting for subsequent data access, ensuring complete error correction and preventing the need for system reboot while managing complexity through automated error handling protocols

Inventive Principle:
Principle #10Preliminary action

3Reliability

If shared memory is used for data communication between nodes, then node independence is reduced and failure impact spreads, but communication efficiency is improved

Engineering Contradiction:
Improvefailure impact isolationVSAvoidcommunication efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system segments memory into shared memory and local memory, allowing nodes to access shared memory for inter-node communication while protecting local memory from direct external access, thus isolating failure impacts to specific segments while maintaining communication efficiency through controlled shared access mechanisms

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10210094B2Information processing system, information processing method and information processing apparatus
Publication Date: 2019.02.19 FUJITSU LTD
  • US10210094B2 patent drawing
  • US10210094B2 patent drawing
  • US10210094B2 patent drawing

AI summary

It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.