Dynamic Cache Coherency Granularity for Multi-Processor Scalability
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Solution Overview
Problem
In multi-processor computing environments, the increasing number of CPU cores leads to scalability issues due to hot spots in shared queues or data structures protected by traditional semaphores, and existing hardware Transactional Memory (TM) solutions face limitations in managing cache coherency and transactional aborts, resulting in inefficiencies and increased latency.
Innovation Solution
A method for dynamic coherency protocol granularity modification is introduced, where cache lines can be configured to operate in full-line or sub-line coherency modes based on coherence miss detection, allowing for adaptive management of cache lines to reduce transactional conflicts and improve scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional semaphores are used to protect shared queues or data structures, then data consistency is maintained, but scalability deteriorates due to hot spots and sub-linear n-way scaling curves
Solution Approach 1:
The patent segments the cache coherency management into fine-grained sub-line portions, allowing different parts of a cache line to be independently managed. This segmentation enables multiple processors to access different portions simultaneously without requiring coarse-grained locking, thereby improving scalability while maintaining data consistency through targeted coherency protocols.
Solution Approach 2:
The patent applies local quality by implementing different coherency management strategies for different portions of cache lines based on their access patterns. High-coherence-miss cache lines are identified and placed in sub-line coherency mode, while other cache lines maintain full-line coherency, optimizing performance for specific localized regions without compromising overall system reliability.
2Productivity
If fine-grained locking is implemented in software to improve scalability, then productivity increases, but device complexity increases and the system becomes more complicated and error-prone
Solution Approach 1:
The patent replaces software-based fine-grained locking mechanisms with hardware-based cache coherency management. The cache control logic automatically manages sub-line coherency for identified high-coherence-miss cache lines, eliminating the need for complex software locking protocols while maintaining scalability and reducing software complexity.
Solution Approach 2:
The patent implements self-service through automatic detection and management of high-coherence-miss cache lines. The coherence miss detection table and cache control logic automatically identify problematic cache lines and apply appropriate coherency modes without requiring software intervention, thereby improving scalability while keeping the system simple to operate.
3Speed
If hardware interconnects with lower latency and higher bandwidth are used, then speed improves, but the latencies are still limited by physical dimensions of chips and systems and the speed of light
Solution Approach 1:
The patent segments cache coherency management to operate at the sub-line portion level rather than full cache line level. This finer segmentation reduces the amount of data that needs to be transferred over interconnects when managing coherency, effectively reducing the impact of physical interconnect limitations and improving effective speed despite fixed physical dimensions.
Solution Approach 2:
The patent applies partial action by implementing coherency management only for specific sub-line portions of cache lines that are identified as high-coherence-miss, rather than managing coherency for entire cache lines. This partial approach reduces interconnect traffic and latency while maintaining necessary coherency, optimizing performance within physical constraints.
4Reliability
If full-line coherency mode is used for cache lines, then data consistency is maintained, but transactional aborts increase due to conflicts, reducing productivity
Solution Approach 1:
The patent segments cache lines into sub-line portions and applies coherency management at this finer granularity. This segmentation allows transactions to proceed without abort when they access different sub-line portions, reducing transactional aborts while maintaining data consistency within each sub-line portion through targeted coherency protocols.
Solution Approach 2:
The patent applies local quality by implementing sub-line coherency mode for specific cache line portions that exhibit high coherence misses, while other portions maintain full-line coherency. This localized approach reduces unnecessary transactional aborts in regions that don't require strict full-line coherency, thereby improving transactional throughput while maintaining consistency where needed.
Data Source
AI summary
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A high-coherence-miss cache line may be placed in sub-line coherency mode. A cache line may be associated with a counter in a coherence miss detection table that is incremented whenever an access of the cache line results in a coherence request. The cache line may be a high-coherence-miss cache line when the counter satisfies a high-coherence-miss criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.