Cache Coherency Interconnect Transaction Management
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Solution Overview
Problem
Current cache coherent interconnects in system-on-chip architectures face inefficiencies due to time-consuming DRAM access, prevention of pipelining for transaction requests with the same identifier, and multiple DRAM read/write operations for cache line writes, which hinder performance in mobile applications and other low-throughput scenarios.
Innovation Solution
A method and system that include an interfacing module capable of generating coherent write requests, managing cache coherency indicators, and performing snoop transactions to invalidate cache lines without sending updated data to DRAM, along with a write compressor to reduce irrelevant data bits, and a mechanism to modify transaction identifiers to prevent pipelining issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a cache coherent interconnect is connected to a DRAM module, then data coherency between cache and memory is maintained, but access time becomes time consuming and efficiency decreases
Solution Approach 1:
The patent extracts the coherency maintenance function from the interconnect path by introducing an independent coherency indicator signal that directly indicates whether the most updated version of data is in the cache. This eliminates the need for time-consuming interconnect transactions to determine data location, as the coherency indicator provides immediate information about cache validity without requiring DRAM access or interconnect traversal.
2Reliability
If a cache coherent interconnect prevents pipelining of transaction requests with the same identifier, then cache coherency is maintained, but transaction processing speed decreases due to sequential servicing
Solution Approach 1:
The patent performs preliminary action by generating coherency indicator signals in advance that indicate the validity state of cache data before transaction requests arrive. This allows the system to pre-determine whether cache lines are valid, enabling pipelined transaction processing without compromising coherency, as the coherency state is already known and does not require sequential verification during transaction handling.
3Reliability
If write operations of portions of a cache line are performed, then data coherency is maintained, but multiple DRAM read and write operations are required increasing complexity
Solution Approach 1:
The patent extracts the coherency verification function from the DRAM operation path by using independent coherency indicator signals that directly indicate cache validity. This allows write operations to portions of cache lines to proceed without requiring multiple DRAM read/write operations, as the coherency state is immediately available through the indicator signals, eliminating unnecessary memory access cycles and reducing operational complexity.
Data Source
AI summary
A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.