Cache Coherency Manager for Multi-Core Domain Partitioning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multiprocessor systems, the disparity between microprocessor clock speeds and memory access times leads to increased latency and power consumption due to heavy coherence traffic among processing cores and I/O devices, as all caches must search for requested data, slowing down the process and consuming more power.
Innovation Solution
A cache coherency manager is implemented to define coherency relationships among processing cores, allowing coherence traffic to flow only between cores with established relationships, reducing unnecessary cache lookups and power consumption by forwarding intervention messages only to cores within the same coherence domain, and maintaining coherency between cores and I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all caches search for requested data to ensure coherence, then data coherence is maintained, but power consumption increases and time is lost
Solution Approach 1:
The patent segments the system into multiple coherence domains by partitioning cores into groups. Instead of all cores searching for every data request, only cores within the same coherence domain search, reducing the search scope while maintaining coherence where needed. This is implemented through a coherency manager that tracks domain memberships and directs requests accordingly.
Solution Approach 2:
The patent applies local quality by making coherence behavior dependent on the specific relationship between requesting and target cores. Cores within the same coherence domain perform local coherence searches, while cores in different domains do not participate. This selective coherence approach optimizes performance for local accesses while maintaining coherence for shared data.
2Reliability
If all caches search for requested data to ensure coherence, then data coherence is maintained, but power consumption increases
Solution Approach 1:
The patent segments the system into multiple coherence domains by partitioning cores into groups. Instead of all cores searching for every data request, only cores within the same coherence domain search, reducing the search scope while maintaining coherence where needed. This is implemented through a coherency manager that tracks domain memberships and directs requests accordingly.
Solution Approach 2:
The patent applies local quality by making coherence behavior dependent on the specific relationship between requesting and target cores. Cores within the same coherence domain perform local coherence searches, while cores in different domains do not participate. This selective coherence approach optimizes performance for local accesses while maintaining coherence for shared data.
3Reliability
If coherence traffic flows between all processing cores, then data coherence is maintained, but system bus bandwidth is consumed
Solution Approach 1:
The patent segments the system into multiple coherence domains by partitioning cores into groups. Instead of all cores searching for every data request, only cores within the same coherence domain search, reducing the search scope while maintaining coherence where needed. This is implemented through a coherency manager that tracks domain memberships and directs requests accordingly.
Solution Approach 2:
The patent extracts unnecessary coherence traffic by removing the requirement for all cores to participate in every coherence protocol operation. Cores outside the relevant coherence domain are excluded from the search and response process, eliminating wasted bandwidth consumption while preserving coherence for the active domain.
Data Source
AI summary
A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as having a coherency relationship. The data defining the coherency relationships between the processing cores is optionally stored in a programmable register. For each source of a coherent request, the processing core targets of the request are identified in the programmable register. In response to a coherent request, an intervention message is forwarded only to the cores that are defined to be in the same coherence domain as the requesting core. If a cache hit occurs in response to a coherent read request and the coherence state of the cache line resulting in the hit satisfies a condition, the requested data is made available to the requesting core from that cache line.