Cache Coherency Management in Multi-Core Image Processors
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Solution Overview
Problem
In multiprocessor systems, the efficiency of cache memory utilization is lowered due to inadequate utilization of spatial and temporal locality in image processing, especially in multi-core systems with more than four cores, where hardware detection of data duplication becomes impractical, leading to reduced cache management effectiveness.
Innovation Solution
A memory management system with a shared memory and cache memory that allows processors to invalidate and write back specified regions immediately before and after processing batches, utilizing a dependency information table and queue to manage execution sequences and maintain coherency between cache and shared memory contents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If hardware for detecting data duplication is used in multi-core systems with more than four cores, then data duplication detection capability is improved, but device complexity increases significantly making it impractical
Solution Approach 1:
The patent replaces hardware-based duplication detection mechanisms with software-based management. The management processor executes instructions to detect and manage data duplication in cache memories across multiple cores, substituting complex hardware circuitry with programmable software logic that achieves the same functional goal without proportionally increasing hardware complexity.
Solution Approach 2:
The patent introduces a management processor as an intermediary between the cache memories and the application processors. This management processor coordinates cache invalidation and data duplication detection across multiple cores, acting as a mediator that simplifies the overall system architecture by centralizing control functions rather than requiring direct hardware interconnections between all cache components.
2Productivity
If cache memory is provided for each core in multi-core systems, then processing performance is improved, but maintaining coherency between cache memories and shared memory becomes more difficult
Solution Approach 1:
The patent implements a feedback mechanism where the management processor monitors cache memory states across multiple cores and dynamically issues invalidation commands or coordination instructions based on detected conditions. This feedback loop enables automatic coherency maintenance without requiring complex static hardware protocols, as the system adapts its control actions based on real-time cache state information.
Solution Approach 2:
The patent enables cache memories to participate in their own coherency management through the software-controlled invalidation process. When data duplication is detected or when data is written to shared memory, the management processor can invalidate specific cache lines or entire cache memories, allowing the cache subsystem to self-regulate its state without external intervention beyond the management processor's coordination.
3Loss of time
If write back system is used to utilize cache memory high speed properties, then write time is shortened, but control to maintain coherency between cache memory and main memory becomes necessary
Solution Approach 1:
The management processor serves as an intermediary that simplifies coherency control in the write-back system. Instead of requiring complex distributed coherency protocols between all cores and main memory, the management processor centralizes the coordination function, issuing invalidation commands to cache memories when main memory writes occur, thereby maintaining coherency with reduced control complexity.
Data Source
AI summary
A memory management system includes a plurality of processors, a shared memory that can be accessed from the plurality of processors, cache memories provided between each processor of the plurality of processors and the shared memory and invalidation or write back of a specified region can be commanded from a program running on a processor. Programs running on each processor invalidate an input data region of a cache memory with an invalidation command immediately before execution of a program as a processing batch, and write back an output data region of a cache memory to the shared memory with a write back command immediately after execution of a program as a processing batch.