Cache Coherency Notification for Device-Processor Data Buffering
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Solution Overview
Problem
Current methods for cache coherency between devices and processors consume processor cycles and increase input/output bus bandwidth due to polling and interrupt signals, which are inefficient and wasteful.
Innovation Solution
An apparatus and method that utilize a buffer module to store data in a non-cache coherent space, update identifiers, and notify the processor of cache incoherence through a coherence notification module, eliminating the need for polling and interrupt signals by maintaining cache coherency between the device and processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polling or interrupt signals are used for communication between electronic devices and processors, then data can be transmitted between devices and processors, but processor cycles and input/output bus bandwidth are consumed
Solution Approach 1:
The system enables self-service communication where the electronic device autonomously manages data buffering and generates coherence notifications without requiring processor intervention through polling or interrupt handling, thereby eliminating wasted processor cycles while maintaining efficient data transmission
Solution Approach 2:
A coherence notification mechanism acts as an intermediary between the electronic device and processor, using cache coherence protocols to automatically signal data availability and changes, replacing the traditional polling/interrupt model and reducing processor cycle consumption
2Productivity
If polling or interrupt signals are used for communication between electronic devices and processors, then data can be transmitted between devices and processors, but input/output bus bandwidth is increased
Solution Approach 1:
The electronic device autonomously manages data buffering in non-cache coherent space and generates coherence notifications only when necessary, eliminating continuous polling traffic and reducing overall I/O bus bandwidth consumption while maintaining efficient data transmission
Solution Approach 2:
The patent extracts the communication notification function from the traditional polling/interrupt model and implements it through cache coherence protocols, separating data transmission from processor notification and reducing unnecessary I/O bus traffic
3Quantity of substance
If data is buffered in non-cache coherent space, then data storage capacity is increased, but cache coherency management becomes more complex
Solution Approach 1:
The system segments memory space into cache coherent space for identifiers and non-cache coherent space for data buffering, allowing large-scale data storage while maintaining simplified coherency management by only tracking coherence for identifier updates rather than entire data buffers
Data Source
AI summary
An apparatus for cache coherency between a device and a processor includes a buffer module that buffers data in a non-cache coherent space of an electronic device communicatively coupled to a processor. The apparatus includes an update module that updates at least one identifier with respect to the buffered data. The at least one identifier is stored in a cache coherent space of the electronic device. The apparatus includes a coherence notification module that notifies the processor of a cache incoherence. The cache incoherence indicates that the cache coherent space of the electronic device that includes the updated at least one identifier differs from a cache coherent space of the processor that includes a copy of the at least one identifier prior to the update.