Cache Coherency Bits for Paced Producer Consumer Data Transfer
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Solution Overview
Problem
Existing data processing systems face challenges in synchronizing producer/consumer data transfers, leading to potential data overwrites or incorrect data reads due to synchronization issues, and require additional hardware mechanisms which increase complexity and cost.
Innovation Solution
Implementing a paced producer/consumer system using a cache that dynamically selects cache lines for paced data transfers by reusing coherency bits to maintain synchronization between producers and consumers, without relying on new hardware mechanisms, by employing a dual protocol mode for normal cache operations and paced data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional producer/consumer data transfer mechanisms (mailboxes, spin-locks, interrupt-based messaging) are used, then data transfer capability is provided, but system complexity and cost increase
Solution Approach 1:
The patent merges the producer/consumer synchronization mechanism with the existing cache structure by utilizing cache lines and coherency bits. The cache lines serve dual purposes: normal cache operations and paced data transfer operations. The coherency bits are reused to indicate both cache coherency states and paced transfer states, eliminating the need for separate synchronization hardware.
Solution Approach 2:
The cache structure is made universal by enabling it to perform both traditional cache functions and paced data transfer synchronization. The same cache lines can be dynamically selected for either normal cache operations or paced transfer operations based on address ranges or sideband signals, making the hardware multi-functional.
2Ease of operation
If traditional producer/consumer data transfer mechanisms are used, then data transfer capability is provided, but synchronization control becomes difficult
Solution Approach 1:
The system implements feedback through the coherency bits that continuously reflect the state of cache lines. When a producer writes to a cache line, the coherency bit is set to indicate the line is being modified. The consumer can check this bit to determine when data is ready, and after reading, the bit is cleared. This feedback mechanism provides automatic synchronization without complex control logic.
Solution Approach 2:
The system uses preliminary action by pre-configuring specific cache lines or address ranges as paced transfer locations. The producer and consumer are预先 assigned specific cache lines for data exchange, and the coherency bits are prepared to track the state of these predetermined locations, enabling synchronized access before actual data transfer occurs.
3Device complexity
If cache lines are dynamically selected for paced data transfers by reusing coherency bits, then synchronization is achieved without new hardware, but protocol management complexity increases
Solution Approach 1:
The system implements dynamics by allowing cache lines to be dynamically selected for paced transfer operations based on address ranges or sideband signals. The same physical cache infrastructure can adapt its behavior based on the operation type, switching between normal cache operations and paced transfer protocols as needed without hardware reconfiguration.
Solution Approach 2:
The system uses parameter changes by interpreting the coherency bits differently based on the operational context. When a cache line is designated for paced transfers, the coherency bits represent paced transfer states rather than traditional cache coherency states. This parameter interpretation change enables the same hardware to support multiple protocols.
Data Source
AI summary
A data processing system including a cache operably coupled to an interconnect and a cache controller. The cache is accessible by each bus initiator of a plurality of bus initiators. The cache includes a plurality of entries. Each entry includes a status field having coherency bits. When an entry of the plurality of entries is in a first protocol mode, the cache controller uses the coherency bits of the entry in implementing a first cache coherency protocol for data of the entry. When the entry is in a second protocol mode, the cache controller uses the coherency bits of the entry in implementing a second cache coherency protocol. The second cache coherency protocol is utilized in implementing a paced data transfer operation between a first bus initiator of the plurality of bus initiators and a second bus initiator of the plurality of bus initiators using the cache entry.